Senior Physical Design Director

Senior Physical Design Director Bangalore We are a well-funded US AI hardware startup building next-generation compute platforms that bring advanced, secure, and sustainable AI from the edge to the cloud. Backed by groundbreaking R&D in computation physics, ultra-efficient circuits, and scalable architectures, we are redefining what’s possible in performance and energy efficiency. Join a team of industry veterans pushing the boundaries of AI and shaping technology that will serve humanity at global scale. and serve as the primary liaison between the India organization and the rest of global leadership. The ideal candidate is a seasoned executive with a strong background in technology, silicon chip design, software, team building, and operations management. Key Responsibilities: Team Building & Leadership: • Develop and execute a comprehensive strategy to establish presence in India. • Recruit top talent • Establish the AI silicon team for in India, focusing on acquiring top talent across , Physical Design, • Foster a collaborative and innovative culture that aligns with global values. Technical Leadership Growth: • Grow technical teams that can contribute to our roadmap and hardware & software products. • Engage deeply in the development and definition of foundational chip architectures , to be well positioned to define and drive future product opportunities. • Lead the India team to collaborate jointly with team-members across world-wide sites with the objective of enabling multiple product and test-chip silicon tapeouts. We are expected to have at least 1 tapeout every year for the next few years – as we ramp up silicon products across different technology nodes and markets. • Building out our IP portfolio across multiple technology nodes – enabling us to license key technologies to adjacent markets including automotive, AR/VR/XR, IoT and datacenters. Technical Execution of Physical Design and Verification (optional in case of PDexpertise): • Drive technical execution across the entire ASIC design flow with specific emphasis on Physical design • Establish physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure • Oversee physical implementation, physical verification, timing closure, documentation and tapeout of complex high performance mixed-signal SOCs (System on a Chip). • Managing PD resources (employees and contractors), to deliver on aggressive tapeout schedules. • Collaborate with a cross-disciplined, multi-site team to identify the issues, get buyin on proposed solutions, and implement the solutions in time for the team to execute to schedule . Qualification and skills: • Hold a BSEE (MSEE preferred) or equivalent experience • 20+ years of experience in large VLSI physical design implementation with exposure to advanced nodes down to 3nm technology. • Successful track record of delivering designs to high volume production. • Familiarity with industry standard P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV), Cadence (Innovus, Tempus, Voltus ) and/or Mentor Graphics. • Experience with the integration of custom analog IP macros such as Serdes, custom memories, CAMs, high-speed IO drivers, PLLs etc. • Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions. • Strong analytical and debugging skills required • Deep understanding of low power implementation initiatives and techniques. Operational Management: • Oversee all aspects of India operations, including office setup, infrastructure, compliance, and vendor management. • Ensure efficient and effective operational processes to support business goals and maintain global alignment. • Develop and manage budgets, ensuring cost efficiency and financial accountability. Contact: Uday Mulya Technologies "Mining The Knowledge Community"