Analog Design Manager

2 months ago

delhi, India Synopsys Inc Full time

Job Description:
We are looking for a sound technical manager to help manage a group of mixed-signal engineers to undertake existing and some next generation DDR/HBM/UCIe PHY IP development. You should have expertise in source-synchronous systems, experience with several designs under their belt who has interests in area of high-speed, DDR/HBM/UCIe memory interface designs. This position will be accountable for Engineering Document creation and maintenance, design reviews and general contributions to development of existing and next-generation PHY interfaces for DDR/HBM/UCIe memory. To be successful in this position, you need to develop and maintain schedules, work in cross-functional settings while being proficient in design & verification. We will rely on your ability to multi-task in client support requests from time to time. You should be familiar with analog mixed-signal simulation strategies and having a good knowledge of Signal Integrity and/or Power Integrity is a plus.

Requirement:
This position requires a minimum of 12+ years of relevant experience, or 8+ years’ experience with a post-graduate degree. You must have knowledge of high-speed analog/digital design areas (preferably, but not limited to transceivers, DDR, etc) and working knowledge of many related areas including DDR, SerDes and/or other communication interfaces.

Skills Needed:
As a technical manager, you need to have leadership qualities, manage developments, and you must have an excellent desire to learn and explore new technologies while demonstrating good review and problem-solving skills. You will be required to mentor junior resources while extracting the best out of senior ones. Prior knowledge and experience in IC CAD tool (HSPICE, Matlab/Simulink) usage is a must; as well as a standard knowledge in exercising mixed-signal verification flow (DRC, LVS, etc).
Extensive experience in STA and timing characterization with solid understanding of static timing concepts, timing constraints, debugging and fixing timing violations
Strong expertise in transistor-level design simulation to debug circuit level issues in timing generation
SiliconSmart/NanoTime experience and strong scripting skills highly desirable
Leadership skills and ability to foster accountability and ownership through hands-on technical leadership with best quality and efficiency
Demonstrate good analysis and problem-solving skills
Good communication and interpersonal skills in interactions to lead development teams

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