DDR / PCIe / NVMe / UCIe - Verification Engineer

Design Verification Engineer - Senior / Lead / Sr. Lead Location: Bangalore / Hyderabad Experience: 4 to 10 Years Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering , Computer Engineering , or a related field. 4+ years of hands-on experience in design verification of high-speed interfaces such as...

POSITION TITLE: Senior Engineer/Engineer – ASIC Design Verification LOCATION: Noida/ Bangalore/ Hyderabad/ Pune/ Chennai/ Ahmedabad ROLE & RESPONSIBILITIES An expert level with developing UVM-based SV test-benches. Highly experienced with defining block, sub-system and SOC top level test plans. Relevant experience with one or more of PCIe,...

POSITION TITLE: Senior Engineer/Engineer – ASIC Design Verification LOCATION: Noida/ Bangalore/ Hyderabad/ Pune/ Chennai/ AhmedabadROLE & RESPONSIBILITIES An expert level with developing UVM-based SV test-benches.Highly experienced with defining block, sub-system and SOC top level test plans.Relevant experience with one or more of PCIe, NVMe, NAND, DDR and...

We’re Hiring | Seniors/Leads/ Managers Design Verification Engineers Are you passionate about IP, Subsystem, and SoC level verification ? Join Mirafra Technologies and be part of an innovative journey in the Semiconductor & VLSI domain , working on cutting-edge projects with a dynamic team! Role: Seniors/Leads/ Managers Design...

We’re Hiring | Seniors/Leads/ Managers Design Verification EngineersAre you passionate about IP, Subsystem, and SoC level verification?Join Mirafra Technologies and be part of an innovative journey in the Semiconductor & VLSI domain, working on cutting-edge projects with a dynamic team!🔹 Role: Seniors/Leads/ Managers Design Verification Engineer🔹...

JD: This role requires expertise in PCIe, CPU, Ethernet, CXL, DDR, and RISC-V technologies. Key Responsibilities: Develop and execute verification plans for hardware designs incorporating PCIe, Ethernet, CXL, DDR, and RISC-V technologies. Design and implement verification environments using SystemVerilog and UVM methodologies. Develop test cases...

JD: This role requires expertise in PCIe, CPU, Ethernet, CXL, DDR, and RISC-V technologies. Key Responsibilities: Develop and execute verification plans for hardware designs incorporating PCIe, Ethernet, CXL, DDR, and RISC-V technologies. Design and implement verification environments using SystemVerilog and UVM methodologies. Develop test cases...

JD:This role requires expertise in PCIe, CPU, Ethernet, CXL, DDR, and RISC-V technologies.Key Responsibilities:Develop and execute verification plans for hardware designs incorporating PCIe, Ethernet, CXL, DDR, and RISC-V technologies.Design and implement verification environments using SystemVerilog and UVM methodologies.Develop test cases to validate...

Job Location: Bangalore/ Hyderabad Notice Period: 15 days to 30 Days Minimum: 4 Years Key Responsibilities: Developing test plans Coding and bring up of asm, c++ tests UVM test bench components coding and maintaining Debugging regression fails Protocol: DDR,PCIE,USB,MIPI, PCIE Preferred Experience: Should have worked on Processor...

Job Location: Bangalore/ HyderabadNotice Period: 15 days to 30 DaysMinimum: 4 YearsKey Responsibilities:Developing test plansCoding and bring up of asm, c++ testsUVM test bench components coding and maintainingDebugging regression failsProtocol: DDR,PCIE,USB,MIPI, PCIEPreferred Experience:Should have worked on Processor based System or Sub-system level...