Principal Digital Design Engineer

5 days ago

bangalore district, India Mulya Technologies Full time

Principal Digital Design Engineer Location: Bengaluru About Omni Design Technologies Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT). Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts. Senior Digital/RTL IC Design Engineer Bangalore Engineering – Digital Circuit Design / Full-time / Principal Digital Design Engineer focusing on the digital datapath of high-performance analog-to-digital and digital-to-analog converters. Job responsibilities include RTL design, verification, behavioral modelling, support and assist with synthesis, timing closure and P&R flow for the digital controller for high performance data converters in cutting edge technologies Qualifications BS/BE/MS/MTech + 8-12 years or equivalent experience in high-performance digital or mixed-signal IC development in advanced CMOS processes Strong foundation in digital design concepts for complex ASICs Hands on experience with the Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc Strong understanding of digital design for mixed signal control loops and designing Verilog code to control analog circuits (e.g. digital backend for ADC, digital PLL, etc) Familiarity with behavioral Verilog code, including wreals Ability to write thorough testbenches Preferred knowledge of Genus, Tempus, Modus and other Cadence tool set used for ASIC design flow Excellent understanding of SystemVerilog Knowledge of SystemVerilog assertions preferred Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

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