Design Verification Engineer
1 week ago
Experience: 5 Years
Location: Bangalore/Hyderabad
Education: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/Electronics
Roles and Responsibilities
DDR Verification: Lead the verification of DDR memory controller and PHY designs, ensuring compliance with DDR standards such as DDR3, DDR4, DDR5, and other memory interface protocols.
Testbench Development: Develop and implement scalable, reusable, and efficient verification environments and testbenches for DDR designs using SystemVerilog, UVM (Universal Verification Methodology), and other industry-standard verification methodologies.
Protocol Compliance: Ensure the DDR design meets protocol specifications, including command, data, and clock synchronization, read/write cycles, burst transfers, refresh cycles, error handling, and power management.
Verification Plan Creation: Develop detailed verification plans based on DDR specifications and requirements, ensuring full coverage of corner cases, timing, and protocol validation.
Simulation & Debugging: Run simulations and debug issues using tools such as Questa, VCS, or ModelSim, applying advanced debugging techniques such as waveform analysis, assertion-based verification, and code coverage.
Regression Testing: Set up and manage regression testing for DDR functionality to ensure continuous validation and early detection of design issues.
Verification Coverage: Achieve high functional and protocol coverage, ensuring that critical aspects of DDR design, including timing constraints, corner cases, and failure scenarios, are thoroughly verified.
Formal Verification: Implement formal verification techniques to validate key components of the DDR design, ensuring correctness in timing and data flow, and verifying the most critical operations.
-
Senior Design Verification Lead
1 week ago
visakhapatnam district, India Eximietas Design Full timeEximietas Design Hiring Senior Design Verification (PCIE) Engineers / Leads / Managers. Experience: 5+ to 15 Years. Location: Bengaluru or Visakhapatnam. Job Description: # Lead SoC Design Verification efforts for complex projects, ensuring successful execution of verification plans. # Develop and implement comprehensive verification strategies,...
-
Senior Design Verification Lead
4 days ago
visakhapatnam district, India Eximietas Design Full timeEximietas Design Hiring Senior Design Verification (PCIE) Leads / Architects / Managers Experience: 10+ Years. Location: Visakhapatnam. Job Description: # Lead SoC Design Verification efforts for complex projects, ensuring successful execution of verification plans. # Develop and implement comprehensive verification strategies, including test plans,...
-
Senior Design Verification Lead
4 days ago
bangalore district, India Eximietas Design Full timeEximietas Design Hiring Senior Design Verification (PCIE) Leads / Managers Experience: 10+ Years. Location: Bengaluru or Visakhapatnam. Job Description: # Lead SoC Design Verification efforts for complex projects, ensuring successful execution of verification plans. # Develop and implement comprehensive verification strategies, including test plans,...
-
Senior Design Verification Lead
2 days ago
bangalore district, India Eximietas Design Full timeEximietas Hiring Senior Design Verification Engineers/Leads (PCIE) Experience - 10+ Yrs. Location - Bengaluru or Visakhapatnam Job Description: Lead SoC Design Verification efforts for complex projects, ensuring successful execution of verification plans. Develop and implement comprehensive verification strategies , including test plans,...
-
Senior Design Verification Leads/Architects
1 week ago
visakhapatnam district, India Eximietas Design Full timeHi All, Greetings' from Eximietas Design....! We are Hiring Senior SOC Design Verification Leads / Architects. Experience: 10+ years Location: Bengaluru or Visakhapatnam. Job Description: We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a strong background in PCIE (Peripheral Component Interconnect...
-
Senior Design Verification Engineer
4 days ago
hyderabad district, India BrainChip Full timeThis is a full-time role for a Senior Design Verification Engineer for Brainchip’s Hyderabad, India Office. This role is responsible for performing functional verification. Key tasks include debugging, ensuring designs meet customer requirements, documenting verification plans, and collaborating with cross-functional teams to improve the verification...
-
Senior Design Verification Engineer
1 week ago
hyderabad district, India ACL Digital Full timeSSOC Design Verification Engineer - Senior / Lead / Sr. Lead Experience: 5 to 12 Years Location: Hyderabad / Bangalore Job Requirement Must have good knowledge on the verification flows Excellent hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC. Experience of...
-
Senior Design Verification Engineer
1 week ago
hyderabad district, India Mulya Technologies Full timeTITLE: Design Verification Engineer LOCATION: GREATER HYDERABAD AREA Company Description We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we...
-
Senior Design Verification Engineer
4 days ago
hyderabad district, India ACL Digital Full timeRTL Verification Experience : 5+years Location : Hyderabad Job Description:Hardware Verification Engineer Basic Job Deliverable:HW Verification Engineer o Responsible for RTL verification, developing Develop SV/UVM testbenches at Top/Sub-system/Block-levels. o Responsible for driving test plan and test spec development and execution, generating...
-
Design Verification Engineer
4 days ago
bangalore district, India ACL Digital Full timeJob Title: Design Verification Engineer Exp Level:4+yrs Location: Bangalore/Hyderabad Job Description: Responsible for ensuring functional correctness of ASIC/SoC designs. Key Task: Develop and execute verification plans for complex digital designs. Methodology: Use UVM/SystemVerilog to create testbenches, write test cases, and debug failures. ...
