High-Speed Analog IP Developer

2 weeks ago

bharatpur, India beBeeAnalogLayout Full time

Senior Analog Layout EngineerWe are seeking an experienced professional to lead the development of high-speed analog IPs. The successful candidate will have a deep understanding of chip-level integration, hierarchy, and physical interfaces.Requirements:8+ years of experience in Analog/Mixed-Signal LayoutStrong expertise in high-speed IPs (SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks)Hands-on experience with ICC2 and top-level integration flowsAbility to run simulations for the blocks being designed (post-layout, extracted)Very detailed understanding of IP-level verification, DRC/LVS/ERC, PEX/RC extraction, signoff decks & reliability checksResponsibilities:Handle chip-level planning and integration of high-speed analog IPsPerform complete analog layout design including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimizationRun post-layout simulations (extracted netlist, corners, Monte Carlo) and ensure correlation with schematicLead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checksDrive complete IP signoff ownership, ensuring zero violations at final GDS deliveryNice to Have:Experience working with advanced nodes (5nm)Exposure to SERDES / PCIe / MIPI / USB high-speed IPsLocation: Remote / India (must support USA/Canada time zone)Travel: Willing to travel to the U.S. for project release (as required)

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