Lead Digital Fault Test Engineer

2 weeks ago

nagpur, India beBeeDigitalFaultTest Full time

Lead Digital Fault Test Engineer Job OpportunityJob Description:We are seeking a seasoned Lead Digital Fault Test (DFT) Engineer to spearhead DFT strategy, architecture, and implementation across complex System-on-Chip (SoC)/Application-Specific Integrated Circuit (ASIC) designs. As a technical leader, you will guide junior engineers, collaborate with cross-functional teams, and ensure top-notch testability and manufacturability of silicon products.Key Responsibilities:Define and drive DFT strategy and architecture for multiple ASIC/SoC projects, ensuring seamless integration and optimal design outcomes.Implement and verify various DFT features, including scan insertion and compression, automatic test pattern generation (ATPG), memory BIST (MBIST), boundary scan, and IJTAG.Oversee the end-to-end DFT flow from Register-Transfer Level (RTL) to gate-level netlist and silicon bring-up, guaranteeing timely completion and quality results.Collaborate closely with RTL, static timing analysis (STA), physical design (PD), and test engineering teams for cohesive and efficient design execution.Generate ATPG patterns, perform fault simulation, and debug test coverage gaps to ensure comprehensive testing.Own DFT signoff, timing closure (DFT-related paths), and automated test equipment (ATE) pattern delivery, driving project success and customer satisfaction.Support silicon bring-up, ATE test vector validation, and yield optimization, applying your expertise to improve product quality.Mentor and guide junior DFT engineers through regular design reviews, training sessions, and hands-on guidance, promoting knowledge sharing and growth.Develop and maintain DFT automation scripts and infrastructure, streamlining processes and enhancing productivity.Required Skills and Qualifications:To succeed in this role, you must possess:A Bachelor's or Master's degree in Electronics, Electrical Engineering, or VLSI Design.At least 7 years of experience in DFT for complex ASIC/SoC designs, with a strong background in digital fault testing.Expertise in scan insertion, compression, ATPG, MBIST, boundary scan, and IJTAG, as well as hands-on experience with industry-leading DFT tools.Strong understanding of RTL design, STA, and synthesis flows, with proficiency in scripting languages (Python, Perl, Tcl) for flow automation.Deep knowledge of silicon test challenges and test coverage improvement techniques.Excellent leadership, team collaboration, and communication skills, with the ability to mentor and guide junior engineers.Why Join Us:As a valued member of our team, you can expect a dynamic and supportive work environment, opportunities for professional growth, and a chance to contribute to cutting-edge projects that shape the future of technology.Additional Information:While we strive to create an inclusive and accessible workplace, please note that this is a general job description and may be subject to change based on business needs. We are committed to equal employment opportunities and welcome applications from qualified candidates regardless of their background.

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