Senior Analog Layout Specialist

7 days ago


madurai, India beBeeAnalog Full time

Job Title: Analog Layout EngineerWe are seeking a highly skilled Senior Analog Layout Engineer to join our team. This individual will be responsible for delivering complex high-speed analog and mixed-signal layout blocks with minimal supervision.Responsibilities:Handle chip-level planning and integration of high-speed analog IPsPerform complete analog layout design including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimization.Run post-layout simulations (extracted netlist, corners, Monte Carlo) and ensure correlation with schematic.Strong understanding of ICC2 flows for complete SoC/top-level integration.Lead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checks.Drive complete IP signoff ownership, ensuring zero violations at final GDS delivery.This role requires a deep technical expertise in chip-level integration, bump planning, and ESD implementation, along with a good understanding of circuit simulation concepts.The candidate must have very strong IP verification knowledge and experience coordinating with foundry teams for signoff, tape-out, and model-related interactions.Requirements:8+ years of solid experience in Analog/Mixed-Signal Layout.Deep expertise in high-speed IPs (SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks).Strong understanding of chip-level integration, hierarchy, and physical interfaces.Hands-on experience with ICC2 and top-level integration flows.Ability to run simulations for the blocks being designed (post-layout, extracted).Very detailed understanding of IP-level verification, DRC/LVS/ERC, PEX/RC extraction, signoff decks & reliability checks.This is an excellent opportunity to work on high-speed analog chip development in advanced TSMC 5nm technology.The ideal candidate will have a strong command of Cadence Virtuoso, PVS, Calibre, and extraction tools.



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