Electronic Systems Designer

1 week ago

davangere, India beBeeAnalog Full time

Senior Analog Layout EngineerWe are seeking a seasoned Senior Analog Layout Engineer with expertise in high-speed analog IPs and top-level integration flows. The ideal candidate will have a deep understanding of chip-level planning, layout design, and post-layout simulations.This is a highly technical role that requires strong ownership of IP development, verification, and delivery. The successful candidate will work closely with foundry teams to ensure seamless IP signoff and tape-out processes.Responsibilities:Handle chip-level planning and integration of high-speed analog IPsPerform complete analog layout design including floorplanning, routing, matching, shielding, EM/IR checks, and parasitic optimizationRun post-layout simulations (extracted netlist, corners, Monte Carlo) and ensure correlation with schematicStrong understanding of ICC2 flows for complete SoC/top-level integrationLead IP verification, including DRC, LVS, ERC, ANT, PEX, and reliability checksDrive complete IP signoff ownership, ensuring zero violations at final GDS deliveryWork closely with foundry teams for PDK clarifications, LVS/DRC rule updates, model issues, and PEX rule discussionsCoordinate with PD, DV, circuit design, and packaging teams for smooth IP-level deliveryRequirements:8+ years of solid experience in Analog/Mixed-Signal LayoutDeep expertise in high-speed IPs (SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks)Strong understanding of chip-level integration, hierarchy, and physical interfacesHands-on experience with ICC2 and top-level integration flowsAbility to run simulations for the blocks being designed (post-layout, extracted)Very detailed understanding of IP-level verification, DRC/LVS/ERC, PEX/RC extraction, signoff decks, and reliability checksProven experience interacting with foundry teams for rule clarifications and IP/tape-out signoffExcellent command of Cadence Virtuoso, PVS, Calibre, and extraction toolsPreferred Qualifications:Experience with advanced nodes (5nm)Exposure to SERDES / PCIe / MIPI / USB high-speed IPsExperience working with global customers

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