Career Opportunity: Chief DFT Architect
6 days ago
Chief DFT ArchitectYou will be responsible for driving DFT architecture, planning, and implementation across complex SoC/ASIC designs.DFT Strategy and Architecture: Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.DFT Implementation and Verification: Lead implementation and verification of DFT features like:Scan insertion and compression (e.g., EDT)ATPG pattern generation and fault gradingMBIST and Logic BIST insertion and validationBoundary scan (IEEE 1149.1/1149.6), IJTAG (1687)The ideal candidate has a B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design with expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Preferred qualifications include experience with hierarchical DFT and low-power DFT methodologies (UPF), exposure to post-silicon validation and failure analysis, familiarity with safety-critical designs (ISO 26262) and functional safety, and experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).Key ResponsibilitiesDevelop and implement DFT strategies for complex SoC/ASIC designs.Lead the implementation and verification of DFT features.Collaborate with cross-functional teams to ensure seamless integration of DFT solutions.Maintain up-to-date knowledge of industry trends and advancements in DFT methodologies.Required Skills and QualificationsB.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Experience with hierarchical DFT and low-power DFT methodologies (UPF).Familiarity with safety-critical designs (ISO 26262) and functional safety.Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET).
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