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Principal Digital Full-Signal Test Engineer

2 weeks ago

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Senior DFT Engineer OpportunityWe are seeking a highly skilled Senior DFT Engineer to drive the development of DFT architecture, planning, and implementation across complex SoC/ASIC designs.DFT Strategy and Architecture:Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.Implementation and Verification:Lead implementation and verification of DFT features like Scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, Boundary scan (IEEE 1149.1/1149.6), IJTAG (1687).Manage End-to-End DFT Flow:Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up.Collaborate with Cross-Functional Teams:Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Mentor Junior Engineers:Mentor and guide junior DFT engineers; conduct design reviews and training sessions.Required Skills and Qualifications:B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.Strong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.Benefits:Opportunity to work on cutting-edge DFT technology.Collaborative work environment with experienced professionals.Professional growth and development opportunities.Other Opportunities:Participate in industry conferences and workshops.Collaborate with cross-functional teams on project-based initiatives.