RTL Design Lead
2 days ago
Job Title: RTL Design Engineer (Mid–Senior Level) Location: [BLR / HYD] Experience: 7– 15 years Employment Type: Full-time Department: Digital Design / SoC Engineering Position Overview We are seeking a highly skilled RTL Design Engineer with strong experience in digital design, architecture bring-up, RTL integration at SoC level, and RTL quality sign-off. The ideal candidate will work closely with architects, verification, physical design, and validation teams to ensure high-quality RTL delivery across multiple IP and SoC programs. Key Responsibilities Architecture & Design Bring-Up Collaborate with system and architecture teams to understand high-level specifications and convert them into micro-architecture and RTL design. Contribute to the development and review of block-level and top-level architecture documents. Drive design partitioning, clock/reset/power domain planning, and interface definition. RTL Design & Integration Develop synthesizable RTL in Verilog or System Verilog for SoC subsystems and IP blocks. Perform RTL integration at subsystem and SoC level, ensuring clean connectivity, interface alignment, and proper clock/reset integration. Own end-to-end RTL integration flow, including configuration management, build, and sanity checks. RTL Quality Checks & Sign-off Run and close lint, CDC/RDC, synthesis, DFT, and other static checks to ensure design readiness. Manage formal checks, low-power (UPF/CPF) validation, and simulation bring-up as part of the sign-off process. Ensure RTL meets quality, performance, and timing closure requirements before release to downstream teams. Cross-functional Collaboration Work closely with Verification, Physical Design, and Firmware teams for seamless design handoff. Participate in design reviews, code walkthroughs, and cross-domain debug activities. Support post-silicon validation by helping analyze functional or timing-related issues. Release Management Own RTL freeze and release management to different stakeholders (DV, PD, Validation). Maintain version control, design documentation, and configuration traceability across project milestones. Required Skills & Experience Bachelor’s or Master’s degree in Electronics, Electrical, or Computer Engineering. 5–12 years of hands-on experience in RTL design and SoC integration. Strong expertise in Verilog/SystemVerilog, SoC architecture, and digital logic design fundamentals. Hands-on experience with tools like: Lint (SpyGlass, Ascent Lint, etc.) CDC/RDC (SpyGlass, Questa CDC, etc.) Synthesis (Design Compiler, Genus, etc.) Formal verification and low-power (UPF/CPF) checks. Familiarity with configuration management tools (Git, Perforce, or similar). Understanding of timing closure concepts, DFT, and simulation environments. Excellent analytical, debugging, and communication skills. Good to Have Exposure to high-performance or low-power SoC architectures. Experience with AXI/AHB/ACE/CHI or other standard bus protocols. Familiarity with Emulation/FPGA prototyping and post-silicon bring-up. Knowledge of EDA automation (TCL, Python, or Make). Please share your jhansi.bv@leadsoc.com for further discussion
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RTL Design Lead
14 hours ago
bangalore district, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | Bangalore Should be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows. Primary Skills:...
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Lead RTL Design Engineer
1 week ago
bangalore district, India ACL Digital Full timeLead RTL Design Engineers Experience Level:10+ years of RTL design and development Job Description: Silicon Design Engineer Location: Hyderabad and Bangalore Basic Job Deliverable: Silicon Design Engineer (RTL Design and Development) o Responsible for RTL design and development o Responsible for generating documents, such as requirements specification,...
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Senior RTL Lead Microarchitect
3 days ago
bangalore, India Eximietas Design Full timeHi All, Greetings' from Eximietas Design ....! We are Hiring RTL Micro Architect Engineers/Leads ...! Job Title: RTL Design Micro Architect. Experience: 10+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US. Job Description: Eximietas Design is seeking an experienced and highly skilled...
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Senior RTL Lead Microarchitect
10 hours ago
bangalore, India Eximietas Design Full timeHi All,Greetings' from Eximietas Design....!We are Hiring RTL Micro Architect Engineers/Leads...!Job Title: RTL Design Micro Architect.Experience: 10+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:Eximietas Design is seeking an experienced and highly skilled RTL Micro...
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Lead/Senior RTL Design
2 weeks ago
bangalore district, India Capgemini Engineering Full timeRole: Lead RTL Design Engineer Experience: 7 to 13 Years Location: Bengaluru Job Description: Should be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have...
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ASIC SOC RTL Design Lead
2 weeks ago
bangalore, India Eximietas Design Full timeHi All,Eximietas: Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains.We are Hiring: ASIC SOC RTL Design Leads/Architect.Experience: 10+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already...
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ASIC SOC RTL Design Lead
2 weeks ago
bangalore, India Eximietas Design Full timeHi All, Eximietas: Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains. We are Hiring: ASIC SOC RTL Design Leads/Architect. Experience: 10+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or...
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ASIC SOC RTL Design Lead
2 weeks ago
bangalore, India Eximietas Design Full timeHi All,Greetings' from Eximietas Design....!We are Hiring ASIC SOC RTL Design Engineer/Leads.Job Title: ASIC SOC RTL Design Engineer/Leads..!Experience: 8+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:Eximietas Design is seeking an experienced and highly skilled ASIC...
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Senior RTL Lead Microarchitect
3 weeks ago
Bangalore Division, India Eximietas Design Full timeHi All, Greetings' from Eximietas Design ....! We are Hiring RTL Micro Architect Engineers/Leads ...! Job Title: RTL Micro Architect. Experience: 8+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US. Job Description: Eximietas Design is seeking an experienced and highly skilled RTL...
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RTL Design Lead
2 weeks ago
bangalore, India L&T Technology Services Full timeRTL Design Engineer with 8+ to 15 of Hands on experiences. • Experience/proficiency in RTL design(Verilog/VHDL) architecture implementation using (coding in) hardware description (RTL) , IP Design, SoC Design and Integration • Should have hands on experience in all the Design aspects, should work independently. • Experience/proficiency in front-end...
