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Staff Design Engineer

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bangalore, India Enphase Full time
Enphase Energy is a global energy technology company and leading provider of solar, battery, and electric vehicle charging products. Founded in 2006, Enphase transformed the solar industry with our revolutionary microinverter technology, which turns sunlight into a safe, reliable, resilient, and scalable source of energy to power our lives. Today, the Enphase Energy System helps people make, use, save, and sell their own power. Enphase is also one of the fastest growing and innovative clean energy companies in the world, with approximately 68 million products installed across more than 145 countries. We are building teams that are designing, developing, and manufacturing next-generation energy technologies and our work environment is fast-paced, fun and full of exciting new projects. If you are passionate about advancing a more sustainable future, this is the perfect time to join Enphase About the role
Enphase is looking for mid-level SoC design engineers with SoC Logic Integration, Synthesis & STA closure experience to join our team in Bangalore India. The team is working on development of our next generation Control ASIC to production in 22nm technology. The ASIC will be a Mixed Signal SOC built around ARM microcontrollers. This position is in our ASIC Engineering Team Reporting to the Senior Director of ASIC Engineering in Bangalore India. What you will do Work on full-chip RTL integration to Synthesized netlist generation.  Work on LINT, CDC, LEC, DFT, Synthesis, STA and ECO implementation with other experienced engineers  Act as liaison with our ASIC backend design services partner.  You will also validate the STA results on the final database delivered by our ASIC partner & DFT to entitlement.
Who you are and what you bring Fair understanding and experience in Synopsys tools like Spyglass, Design Compiler, Primetime. Ability to create the timing constraints based on specification. RTL Integration of SoC/Subsystems from IPs, ability to debug the issues in logic verification, act as liaison between Design and Place and Route teams.  Knowledge of all the Soft IP collateral and deliverables eg: Lint, CDC, Synthesis, Timing constraints, LEC & ATPG. Experience and ability to bring complex SOCs into the physical world and into production. #SoC Integration #ARM #Synthesis #Timing Constraints #STA #DFT. Prior hands on work experience of at least 6 years in Logic IP/SoC design.