Senior Design Verification Engineer

3 days ago

bangalore, India Blueberry Semiconductors Full time

Job Title: Senior Verification Engineer – UVM/IP/SOCLocation: [Bengaluru]Job Type: Full-TimeExperience Level: 4 to 6+ YearsEducation: B.Tech/ B.E, M.Tech, Electrical/Electronics Engineering, or related fieldPREFERABLE: Immediate Joiners are preferred Job Description:We are seeking a highly motivated and experienced Senior Verification Engineer to join our IP/SOC verification team. The ideal candidate will have a strong background in UVM-based testbench development, System Verilog, and hands-on verification of complex IP and SoC designs. You will play a key role in ensuring the functional correctness and robustness of our next-generation products.Key Responsibilities:Own the development and maintenance of UVM-based verification environments for IP/SOC-level designs.Architect and implement testbenches, including test plans, scoreboards, and System Verilog Assertions (SVA).Develop and execute detailed verification plans aligned with design specifications.Ensure comprehensive functional coverage and drive coverage closure.Debug simulation failures and drive root-cause analysis in collaboration with design teams.Work with industry-standard protocols such as PCIe, CXL, UCIe, and AMBA (AXI, AHB, APB).Utilize version control tools such as Perforce to manage codebase.Create scripts using Python, TCL, or other scripting languages to automate verification tasks.Required Skills & Experience:6+ years of experience in ASIC/IP/SOC verification.Strong hands-on experience with System Verilog and UVM methodology.Proven expertise in writing and debugging System Verilog Assertions (SVA).Solid understanding of industry-standard protocols (PCIe, CXL, UCIe, AMBA).Proficient in debugging simulations using industry-standard tools.Experience with version control systems like Perforce.Scripting experience in Python, TCL, or similar is a strong plus.Preferred Qualifications:Experience working in complex SoC\IP projects with multi-protocol interfaces.Exposure to formal verification techniques and tools.Familiarity with EDA tools from Synopsys, Cadence, or Mentor Graphics.Why Join Us?Be part of a cutting-edge engineering team driving innovation in next-generation IP/SOC design.Work with industry veterans and a dynamic, collaborative team.Competitive salary, benefits, and growth opportunities.Interested candidates can apply directly with their updated resume and cover letter.

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