Lead Physical Design Engineer

Responsibilities :  Develop and support automated physical design (PD) CAD flows, including floorplanning, placement, and routing optimization.  Customize and optimize physical design flows using industry-standard EDA tools (such as Synopsys ICC2, Cadence Innovus).  Collaborate with the design and CAD teams to improve PD workflows,...

Responsibilities :  Minimum 8+ years of experience and with 0 - 30 Notice period  Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs.  Define and drive physical design strategies to meet aggressive performance, power, and area targets.  Perform efficient Clock planning and...

Hi, I am excited to announce that #Tessolve is hiring for Experienced candidates to join our dynamic team in #Bangalore and #Chennai! Responsibilities: Experience in leading & managing the physical design team to deliver high-quality physical design solutions for complex ASIC/SOCs. Experience in the entire physical design flow: floor planning,...

SALARY : 20LPA - 45LPA We are recruiting One of Our Indian Based MNC ClientClient - Indian Based MNC ClientType of Job - Full Time/Direct hire Type - HybridNotice Period - Not more than 45 Days with serving candidatesRole : Physical Design (PD) LeadExperience : 10+ YearsLocations : BangaloreMandatory Skills : Physical Design ExperienceJob Descriptions :-...

Responsibilities :  Minimum 8+ years of experience and with 0 - 30 Notice period  Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs.  Define and drive physical design strategies to meet aggressive performance, power, and area targets.  Perform efficient Clock planning and...

Wipro Hiring Physical Design Engineers / Leads Experience : Min 5-20 Years. In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. · Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower...

Responsibilities : Minimum 8+ years of experience and with 0 - 30 Notice period Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for HighSpeed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and areatargets. Perform efficient Clock planning and distribution to...

PNR Lead EngineersWork Location: BangaloreExperience: 7+YearsTechnical Skills:Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage designDeep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closureResponsible...

e Infochips (An Arrow Company) Hiring Physical Design Engineer Experience - 4+ Years Location- Bangalore/Hyderabad/Ahmedabad/Noida/Chennai Job description is as below: * Block level Physical Design Implementation from RTL to GDSII or Netlist to GDSII, * Block level Physical Signoff, * Block level Timing Signoff and ECO generation. * Block level...

E Infochips (An Arrow Company) Hiring Physical Design Engineer Experience - 4+ Years Location- Bangalore/Hyderabad/Ahmedabad/Noida/Chennai Job description is as below: * Block level Physical Design Implementation from RTL to GDSII or Netlist to GDSII, * Block level Physical Signoff, * Block level Timing Signoff and ECO generation. * Block level...

Responsibilities:  Minimum 8+ years of experience and with 0 - 30 Notice period  Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for HighSpeed Advance ASICs.  Define and drive physical design strategies to meet aggressive performance, power, and areatargets.  Perform efficient Clock planning and distribution to...

Responsibilities :  Minimum 8+ years of experience and with 0 - 30 Notice period  Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs.  Define and drive physical design strategies to meet aggressive performance, power, and area targets.  Perform efficient Clock planning and...

About the Company Bitsilica is a company that specializes in physical design implementation of large ASIC’s. Our mission is to provide cutting-edge solutions in the semiconductor industry while fostering a culture of innovation and collaboration. About the Role We are looking for a candidate with relevant work experience in physical design...

eInfochips (An Arrow Company) Hiring Physical Design Engineer Experience - 4+ Years Location- Bangalore/Hyderabad/Ahmedabad/Noida/Chennai Job description is as below: * Block level Physical Design Implementation from RTL to GDSII or Netlist to GDSII, * Block level Physical Signoff, * Block level Timing Signoff and ECO generation. * Block level...

Hi, I am excited to announce that #Tessolve is hiring for Experienced candidates to join our dynamic team in #Bangalore and #Chennai! Responsibilities: Experience in leading & managing the physical design team to deliver high-quality physical design solutions for complex ASIC/SOCs. Experience in the entire physical design flow: floor planning,...

We need an experienced Physical Design Engineer to join our ATD team. The candidate should have a strong background in back-end design of ASIC/So C chips. The ideal candidate will have a bachelor’s or master’s degree in Electrical Engineering or a related field. Requirements 1 - 2 Years of experience in physical design Bachelor’s or master’s...

Role : PD Lead Exp : 7+ years Location : Bangalore BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design Detailed knowledge of EDA tools and flows, Fusion compiler based RTL2 GDS flow is desired Should be able to handle Full chip Pn R (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep...

Role : PD Lead Exp : 7+ years Location : Bangalore BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design Detailed knowledge of EDA tools and flows, Fusion compiler based RTL2GDS flow is desired Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep...

Role : PD LeadExp : 7+ yearsLocation : BangaloreBE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical DesignDetailed knowledge of EDA tools and flows, Fusion compiler based RTL2GDS flow is desiredShould be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage designDeep understanding...

Job Title: Physical Design Engineer Location: Bangalore/ Hyderabad Job Summary: We are seeking a skilled and detail-oriented Physical Design Engineer to work on the physical implementation of complex ASICs and So Cs. The role involves performing various backend design tasks, including floorplanning, placement, routing, timing closure, and power...