Digital Fault Tolerance Architect

5 days ago

jaipur, India beBeeDftEngineer Full time

Job Opportunity: Lead DFT EngineerWe are seeking an experienced individual to lead our Digital Fault Tolerance (DFT) strategy and architecture for complex System-on-Chip (SoC)/Application-Specific Integrated Circuit (ASIC) designs.Define and drive DFT strategy and architecture for multiple SoC/ASIC projectsImplement and verify DFT features such as scan insertion and compression, ATPG pattern generation, and boundary scanMentor junior engineers and collaborate with cross-functional teamsThe ideal candidate will have a strong background in electronics, electrical, or VLSI design, with expertise in DFT tools such as Synopsys, Siemens EDA, and Cadence. They will also have strong knowledge of RTL design, Static Timing Analysis (STA), and synthesis flows, as well as proficiency in scripting languages such as Python, Perl, and Tcl.Requirements:Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design7+ years of experience in DFT for complex ASIC or SoC designsExpertise in DFT tools such as Synopsys, Siemens EDA, and CadenceStrong knowledge of RTL design, STA, and synthesis flowsProficiency in scripting languages such as Python, Perl, and Tcl

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