BITSILICA | IP

4 days ago

bangalore, India BITSILICA Full time

About the job

Seeking experienced IP/SOC DV (Design verification) Lead/Manager. The Candidate will be responsible for all aspects of the Design Verification including schedule, test code, test bench development, and documentation. The candidate will be additionally responsible for all emulation/prototyping and low-level driver software development.


Minimum Qualifications:


  • 10+ years of experience in Design Verification of high performance SoCs
  • Knowledge of System Verilog, C language, UVM, UPF and Verification IP environments
  • Expertise in scripting languages like Python, Tcl/Tk, Perl etc
  • Experience with major EDA tool vendor tools like Synopsys/Cadence/Tessent is desirable. Hands on knowledge of Synopsys Tools is preferable
  • Hands on knowledge of bus architecture like AXI/AHB/equivalent protocols, CPU cores and peripherals
  • Excellent analytical and problem-solving skills, with great execution focus
  • Good leadership capabilities to lead a team of engineers and contractors to accomplish the organization goals
  • Independently code, debug and perform verification tasks for high performance designs and mentor the team
  • Collaborate with leadership team to hire engineers and contractors required to execute the project in collaboration with the leadership team

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