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Senior Engineer II-Implementation

2 months ago

bangalore, India Microchip Technology Full time

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B) global organization? We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our ; we affectionately refer to it as the and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over without a great team dedicated to empowering innovation. People like you.

Visit our page to see what exciting opportunities and company await

Job Description:

Job Description:

The Wireless Solutions Group (WSG) is seeking an Implementation Engineer to support SOC development for our next generation, mixed signal, wireless products. The role will include driving synthesis, static timing analysis, logical equivalence checks, PPA comparison studies using an industry leading ASIC design flow. It will require a proactive candidate with a proven record of success in cross functional and cross site team environments.

Key Responsibilities:

Implementation engineer supporting WSG Silicon Development based in Bangalore, India Drive and optimize STA methodologies for Microchip’s wireless SoC Development. Drive SoC timing budgeting, constraint analysis, optimization, and sign-off timing closure Drive and optimize Formal Verification (logic equivalency) methodologies. Drive full chip Floorplanning activity Drive PPA benchmarking activities to identify the best suited IP libraries (standard cells, memories, IOs) amongst several cutting-edge IP solutions offered by IP providers. Work with architecture on cost analysis/die-size estimation in early stages and propose area reduction techniques Interface with design, analog design, verification, product, marketing and other teams to drive towards a successful SoC development Participate in SoC Implementation planning and scheduling. Continuously improve RTL-to-GDS tool flows and methodologies.

Requirements/Qualifications:

Required Skills:

Expertise in Static Timing Analysis, Formal Verification and Synthesis preferably with Synopsys tools. Expertise in full chip Floorplanning Preferable to have hand-on experience in PnR flow, IR Drop Analysis, Physical Verification with Industry standard tools Experience with low-power implementation techniques (UPF). Proficient in common scripting languages (Perl, Python, Tcl, csh, etc.) Knowledge of Design Database Management tools such as DesignSync and revision control tools such as GIT, Perforce, and CVS. Solid Written and Verbal Communication skills Experience working with cross functional global teams


Desired Skills:

Experience with ARM/MIPS processor based subsystem Knowledge of Chip level Design and Integration activities Knowledge and exposure to complete SOC RTL to GDS to silicon release flow is desired Experience working on WiFi, WLAN, or Bluetooth products

Required Education:
B.Tech or M.Tech in Electrical/Electronic Engineering with 6+ years of experience, M.Tech preferred

Travel Time:

0% - 25%