DFT Architect

Senior Design for Test (DFT) StrategistThe Senior DFT Strategist is a key technical leader responsible for driving the design for test architecture, planning, and implementation across complex System-on-Chip (SoC)/Application-Specific Integrated Circuit (ASIC) designs.This individual will be instrumental in defining and driving the DFT strategy and architecture, leading the implementation and verification of DFT features, managing the end-to-end DFT flow, collaborating with cross-functional teams, performing pattern generation, fault simulation, and debug test coverage gaps, owning DFT signoff, timing closure (DFT-related paths), and Automated Test Equipment (ATE) pattern delivery.The ideal candidate should have hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX Siemens EDA: Tessent ScanPro, MBIST, IJTAG Cadence/others: Modus, Encounter Test. Additionally, they should have a strong understanding of RTL design, Static Timing Analysis (STA), and synthesis flows, as well as proficiency in scripting languages (Python, Perl, Tcl) for flow automation.Key Responsibilities:Define and drive DFT strategy and architecture for complex SoC/ASIC designs.Lead the implementation and verification of DFT features.Manage the end-to-end DFT flow.Collaborate with cross-functional teams to ensure smooth integration of DFT components.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Required Skills and Qualifications:Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Strong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.