Senior Analog Layout Expert

2 weeks ago

nellore, India beBeeExpert Full time

Job DescriptionAs a Senior Analog Layout Engineer, you will play a crucial role in designing and integrating high-speed analog IPs at the chip level. Your expertise in ICC2-based top-level integration, IP verification, and simulation will enable seamless IP delivery.You will be responsible for leading chip-level planning and integration of high-speed analog IPs, executing complete analog layout design including floor planning, routing, device matching, shielding, EM/IR checks, and parasitic optimization.Additionally, you will own the entire IP verification process: DRC, LVS, ERC, ANT, PEX, and reliability checks. You will ensure zero-violation GDS delivery for IP signoff.Required Skills and QualificationsMandatory hands-on experience with TSMC 5nm.Strong understanding of ICC2 flows for complete SoC/top-level integration.Ability to run extracted and post-layout simulations for designed blocks.What We OfferWe provide a dynamic work environment that encourages innovation and collaboration. Our team is committed to delivering high-quality results, and we are looking for individuals who share our passion for excellence.Other InformationThis role requires 8+ years of proven experience in Analog/Mixed-Signal Layout. You should have deep expertise in high-speed IPs: SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks.Proficiency in Cadence Virtuoso, PVS, Calibre, and extraction tools is essential. Additionally, you should have in-depth knowledge of DRC/LVS/ERC, PEX & RC Extraction, and Signoff decks and reliability checks.

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