Senior Analog Designer

2 weeks ago


kurnool, India beBeeAnalog Full time

Job Overview:We are seeking an experienced Analog Layout Engineer to join our team. The ideal candidate will have a strong background in designing and integrating high-speed analog IPs at the chip level.Key Responsibilities:Analog Layout & Integration: Lead chip-level planning and integration of high-speed analog IPs. Execute complete analog layout design including floor planning, routing, device matching, shielding, EM/IR checks, and parasitic optimization.IP Verification & Signoff: Own the entire IP verification process: DRC, LVS, ERC, ANT, PEX, and reliability checks. Ensure zero-violation GDS delivery for IP signoff.Requirements:Mandatory hands-on experience with TSMC 5nm.Strong understanding of ICC2 flows for complete SoC/top-level integration.Ability to run extracted and post-layout simulations for designed blocks.8+ years of proven experience in Analog/Mixed-Signal Layout.Deep expertise in high-speed IPs: SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks.Proficiency in Cadence Virtuoso, PVS, Calibre, and extraction tools.Benefits:Good understanding of chip-level hierarchy, integration, and physical interfaces.Strong sense of ownership in IP development, customer communications, and documentation.ExperienceDRC/LVS/ERCPEX & RC ExtractionSignoff decks and reliability checksFoundry coordinationTape-out requirements



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