Lead SoC Verification engineer

1 day ago

bangalore district, India Eteros Technologies Full time

Eteros Technolgies is Seeking a Senior/ Lead Verification Engineer with strong expertise in simulation environment migration, debugging, and coverage analysis . The role involves migrating IP and SoC-level verification environments between Cadence Xcelium and Synopsys VCS , ensuring simulation stability, functional correctness, and coverage closure for complex designs involving ARM Cortex, PCIe , and other high-speed protocols. Key Responsibilities Environment Migration: Migrate SystemVerilog/UVM testbenches between Xcelium and VCS. Resolve simulator-specific issues (macros, DPI, coverage differences) . PCIe & High-Speed Protocol Verification: Verify PCIe at IP/SoC levels – LTSSM bring-up, PIPE/PHY interface, protocol compliance. Debug link training, power management, and reset issues. Integrate and analyze VIPs (Synopsys/Cadence). Gate-Level Simulation (GLS): Set up and run GLS with/without timing. Debug timing violations, X-propagation, and reset mismatches. Correlate RTL vs GLS for sign-off. Automation & Integration: Automate regressions using Makefiles, Python, Perl on LSF/Jenkins. Integrate IPs into ARM Cortex-based SoC environments. Debug & Coverage: Debug UVM/DUT interface failures and analyze assertion, protocol, and timing issues. Track and close functional/code coverage using IMC, Verdi, or Verisium tools. Required Skills Languages: SystemVerilog, UVM, C/C++ (DPI), Python, Shell, Perl Tools: Xcelium, VCS, SimVision, Verdi, Verisium, IMC Protocols: PCIe, AMBA, I3C/I2C, SPI, UART, GPIO Expertise: Debugging, signal tracing, coverage analysis, GLS sign-off Qualifications B.E./B.Tech or M.E./M.Tech in ECE/EE 8–12 years of experience in functional verification Strong PCIe and ARM-based SoC background Experience with coverage closure and debug automation

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