Sr. Design Verification
3 weeks ago
Design Verification Engineer
Experience. 5+ Years
NP- Immediate- 30 days
Experience on either IP level verification (protocol verification) or SOC-level verification
· Proficiency in Verilog, System Verilog, VHDL, C, System C, SV-UVM
· Understanding of code coverage, functional coverage, assertions, cover groups etc
· Protocols : PCIe, CXL, Ethernet, (High Speed protocols preferred)
· Testbench/ Environment/ Case development, randomization, regression test planning and development.
· Simulation and debug of RTL/PA-RTL/GLS/PA-GLS.
· Understanding of PHYs like SERDES PHY, DDR/LPDDR PHYs.
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Sr. Design Verification
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