DFT Architect

Complex IP Development RoleWe are seeking highly motivated individuals with strong technical skills and experience in leading-edge tools like Synopsys, Cadence, or Mentor.Key Responsibilities:Design and deliver advanced IPs using cutting-edge techniques and methodologies.Develop and implement architectures for design-for-testability, ATPG, simulation, and global logic synthesis.Experience in working with Synopsys, Cadence, or Mentor tools like Tetramax, Modus, Tessent, and Design Compiler.Hands-on expertise in automated test pattern generation, scan insertion, and simulation.A deep understanding of JTAG is an added advantage.Strong debugging skills with simulation tools.Excellent documentation skills for architecture specifications and system integration documents.Proficiency in scripting languages like Perl, Python, Shell, or TCL.About Our WorkTessolve Semiconductors delivers end-to-end solutions from product development to delivery. With a global presence and over 2500 employees worldwide, we provide a unique combination of pre-silicon and post-silicon expertise. Our state-of-the-art silicon and system testing labs offer a one-stop-shop solution with comprehensive hardware and software capabilities.