IP Verification Engineer

1 week ago


bangalore, India ACL Digital Full time

Job Title:IP Verification Engineer – UVM verificationExp Level:4+ yrsLocation:Bangalore/HyderabadJob Description:System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol. Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers.Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.Basic Job Deliverable:Setup verification environment and bring up simulations with various simulations such as VCS / Questa / Xcellium / RivieraSV/UVM Functional verificationExpertise in Vivado for simulation debugsQualification:B.E/M.E/M.TechInterested can Share CV to sharmila.b@acldigital.com



  • Bangalore, India ACL Digital Full time

    Job Title :IP Verification Engineer – UVM verification Exp Level:4+ yrs Location:Bangalore/Hyderabad Job Description:System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip...


  • bangalore, India ACL Digital Full time

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  • bangalore district, India ACL Digital Full time

    Job Title :IP Verification Engineer – UVM verification Exp Level:4+ yrs Location:Bangalore/Hyderabad Job Description:System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip...


  • bangalore district, India ACL Digital Full time

    GFx IP Verification Engineer Ramp up on the GFx IP and the verification infrastructure. Debug C++ based testcases using logs and waveforms. Regression debug and root cause, raise JIRAs and verify the fixes Coverage analysis. Port C++ tests to PSS. Debug and fix the PSS tests to have the same result as C++ tests. 4+ years of design verification experience....


  • bangalore, India ACL Digital Full time

    GFx IP Verification EngineerRamp up on the GFx IP and the verification infrastructure.Debug C++ based testcases using logs and waveforms.Regression debug and root cause, raise JIRAs and verify the fixesCoverage analysis.Port C++ tests to PSS.Debug and fix the PSS tests to have the same result as C++ tests.4+ years of design verification experience.Experience...

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