Digital Fault Tolerance Architect

2 days ago

kolkata, India beBeeDftEngineer Full time

Key Responsibilities:    Define and drive digital fault tolerance (DFT) strategy and architecture for multiple complex system-on-chip (SoC) projects.    Lead the implementation and verification of DFT features, including scan insertion and compression, automatic test pattern generation (ATPG), memory built-in self-test (MBIST), logic built-in self-test (LBIST), boundary scan, and IEEE 1149.1/1149.6 standards.    Manage the end-to-end DFT flow from register-transfer level (RTL) to gate-level netlist and silicon bring-up.    Collaborate with RTL, static timing analysis (STA), physical design (PD), and test engineering teams for seamless integration.    Perform pattern generation, fault simulation, and debug test coverage gaps.    Own DFT signoff, timing closure (DFT-related paths), and automated test equipment (ATE) pattern delivery.    Support silicon bring-up, test vector validation on ATE, and yield optimization.Requirements:    B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.    7+ years of experience in DFT for complex SoC designs.    Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.    Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.    Strong knowledge of RTL design, STA, and synthesis flows.    Proficient in scripting languages (Python, Perl, Tcl) for flow automation.    Deep understanding of silicon test challenges and test coverage improvement.    Strong leadership, team collaboration, and communication skills.

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