Expert High-Speed Analog Layout Design Specialist

1 week ago


ghaziabad, India beBeeAnalog Full time

**Senior Analog Layout Engineer Role Overview**This is a highly challenging and rewarding role for an experienced Senior Analog Layout / IP Delivery Engineer.**Key Responsibilities:**Analog Layout & Integration: Lead chip-level planning and integration of high-speed analog IPs, execute complete analog layout design including floor planning, routing, device matching, shielding, EM/IR checks, and parasitic optimization.IP Verification & Signoff: Own the entire IP verification process: DRC, LVS, ERC, ANT, PEX, and reliability checks, ensure zero-violation GDS delivery for IP signoff.Cross-Functional Collaboration: Coordinate with PD, DV, circuit design, packaging, and integration teams for seamless IP delivery, prepare and deliver comprehensive IP documentation, abstracts, verification reports, and final GDS.Process & Technology Expertise: Mandatory hands-on experience with TSMC 5nm, strong understanding of ICC2 flows for complete SoC/top-level integration, ability to run extracted and post-layout simulations for designed blocks.**Required Skills & Qualifications:**8+ years of proven experience in Analog/Mixed-Signal Layout.Deep expertise in high-speed IPs: SERDES, PLL, ADC/DAC, Tx/Rx, clocking blocks.Strong understanding of chip-level hierarchy, integration, and physical interfaces.Proficiency in Cadence Virtuoso, PVS, Calibre, and extraction tools.In-depth knowledge of DRC/LVS/ERC, PEX & RC Extraction, signoff decks and reliability checks.Experience interfacing with foundry teams for rule clarifications and tape-out signoff.**Good to Have:**Experience with other advanced process nodes (7nm/3nm).Exposure to SERDES/PCIe/MIPI/USB high-speed IPs.Experience working with global clients.



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