Chief Architect of Digital Fault Tolerance

6 days ago

thane, India beBeeDigitalFaultTolerance Full time

Job Title: Chief Architect of Digital Fault ToleranceWe are seeking a visionary Chief Architect of Digital Fault Tolerance to spearhead the development of cutting-edge digital fault tolerance architectures for complex System-on-Chip (SoC) and Application-Specific Integrated Circuit (ASIC) designs.Key Responsibilities:Design and implement comprehensive digital fault tolerance strategies and architectures for multiple high-profile ASIC/SoC projects.Develop and verify innovative digital fault tolerance features, including scan insertion, compression, automatic test pattern generation, fault grading, memory built-in self-test (MBIST), logic built-in self-test (LBIST), boundary scan, and integrated joint test action group (IJTAG).Oversee the entire digital fault tolerance workflow, from register transfer level (RTL) to gate-level netlist and silicon bring-up.Collaborate closely with cross-functional teams to ensure seamless integration and successful project delivery.Perform advanced pattern generation, fault simulation, and debug test coverage gap analysis.Own the digital fault tolerance signoff process, timing closure, and at-speed test vector validation.Support silicon bring-up, yield optimization, and provide technical guidance to junior engineers through design reviews and training sessions.Develop and maintain automated digital fault tolerance scripts infrastructure.Requirements:Deep expertise in digital fault tolerance architecture, design, and implementation.Excellent understanding of SoC/ASIC design flows, including RTL, synthesis, place-and-route, and physical verification.Strong knowledge of digital fault tolerance features, including scan insertion, compression, ATPG, fault grading, MBIST, LBIST, boundary scan, and IJTAG.Proven experience in managing cross-functional teams and collaborating with engineering, product, and program management stakeholders.Excellent communication and interpersonal skills.Benefits:Opportunity to work on high-profile ASIC/SoC projects.Collaborative and dynamic work environment.Professional growth and development opportunities.Competitive compensation package.Others:Eligibility to work in the United States.Background check required.

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