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Mulya Technologies | Senior Principal Physical Design Engineer
1 month ago
www.omnidesigntech.com
Senior Principal Physical Design Engineer ( with exp in 3nm )
About Omni Design Technologies
Omni Design Technologies is a leading provider of high-performance, ultra-low power IP cores, from 28nm down through advanced FinFET nodes, which enable differentiated system-on-chip (SoC), in applications ranging from 5G, wireline and optical communications, LiDAR, radar, automotive networking, AI, image sensors, and the internet-of-things (IoT). Our data converter (ADC and DAC) IP cores range from 6-bit to 14-bit resolution and from a few MSPS to more than 100 GSPS sampling rates. Omni Design, founded in 2015 by semiconductor industry veterans, has an excellent track record of innovation and collaboration with customers to enable their success. The company is headquartered in Milpitas, California with additional design centers in Fort Collins-Colorado, Bangalore-India, Hyderabad-India, Dublin-Ireland, Boston-Massachusetts.
Bangalore
Bangalore
Full-Time /
We are looking for a Principal experienced place-and-route engineer, who is capable of driving the required digital backend flows to create our designs. The ability to work closely with rtl design team to understand partition architecture and drive physical aspects early in design cycle in a key feature of this role
Qualifications
- You should have physical design experience, with recent successful tapeouts in deep submicron technology and FinFet technology.
- Knowledgeable in partition level P&R implementation, including floorplanning, clock & power distribution, timing closure, physical & electrical verification
- Strong knowledge of PD construction & analysis flows and methodology
- Ability to execute to stringent schedule & die size requirements
- Strong communication skills
- Experienced in industry standard tools, understand their capabilities and underlying algorithms
- Experience with large SOC/IP designs with frequencies in excess of 500Mhz
- Ability to resolve design and flow issues related to physical design, identify potential solutions and drive execution
Education and Experience
- B.E./B.Tech./M.E./M.Tech in VLSI
- Minimum of 12 years of working experience in PnR flow of a product company.
- Candidate must have working experience in 7nm FF and on lower nodes.
Detailed responsibilities and skills
- Perform Floor-planning and Placement, CTS, Routing.
- LVS, DRC and Antenna checks and Generation of GDSII and .lib
- Reliability checks like EM violations check and Signal Integrity issues like crosstalk
- Perform physical verification, IR drop analysis, and generating SPEF
- Knowledge of full RTL to GDSII flow (Floorplan, CTS, PnR, DRC/LVS, SI, IR Drop )
- Hands-on experience with Cadence PnR tools, Floorplanning, IR Drop and Physical verification
- have good understanding of verilog/VHDL
- Exposure to low power techniques
- Knowledge of tcl and Python scripting is a must
We are looking for trailblazers ...
We strongly believe that the pace of the ongoing hardware revolution will be greatly accelerated by Design’s IP cores and the rapidly emerging semiconductor embedded design business ecosystem.
we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring our vision to fruition.
If you are interested in making an impact as part of a young, fast growing, cutting edge technology company, please reach out to us.
We are a equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence.
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
