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bangalore, India ACL Digital Full timeJob Title:Lead Physical Design Engineer Experience:7+ Years Location:Bangalore/Hyderabad Employment Type:Full-time Industry:Semiconductors / ASIC / VLSI / SoC Design Job Summary: We are seeking a highly experienced and technically strongLead Physical Design Engineerto drive RTL-to-GDSII implementation for complex SoC or block-level designs. The ideal...
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Lead Physical Design Engineer
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Physical Design Engineer Lead
3 weeks ago
Greetings Hiring: Physical Design Engineer Lead – Bangalore (4 Days WFO) Experience Range: 13.5–20 Years Industry: Semiconductors / VLSI / ASIC Design Employment Type: Full-Time Job Title: Physical Design Engineer Location: Bengaluru, India Job Summary We are looking for an experienced Physical Design Engineer to join our chip development team. You will be responsible for implementing and optimizing the physical layout of complex ASICs from RTL to GDSII , working closely with RTL, Verification, DFT, and other cross-functional teams to ensure successful tape-out of high-performance, low-power silicon designs. Key Responsibilities Execute physical design tasks including floorplanning, power planning, placement, CTS, routing , and physical verification (LVS/DRC) . Work on timing closure using STA tools and fix violations across multiple PVT corners. Perform IR drop and EM analysis , and drive fixes for power integrity. Collaborate with RTL, DFT, packaging, and manufacturing teams. Debug issues across PnR, DRC/LVS, and timing flows , providing RCA and solutions. Contribute to flow development, automation , and overall design efficiency improvements. Required Qualifications BE/BTech in Engineering or equivalent. 7+ years of experience in ASIC physical design with proven tape-out experience. Strong hands-on expertise with tools such as Innovus, ICC2, PrimeTime, Voltus, Calibre . Solid understanding of timing, SI, IR drop, physical verification . Good scripting skills in TCL, Python, or Perl . Excellent problem-solving and communication skills. ✨ Preferred Qualifications Experience with hierarchical design methodologies . Exposure to low-power design (UPF) . Experience with advanced nodes (7nm, 5nm or below) . Note: For candidates with 10+ years experience , expertise in 7nm–10nm is required. Work Mode: Bangalore – 4 Days WFO
