DFT Expert Lead

3 days ago

salem, India beBeeDesign Full time

Job Title: Senior Design For Testability EngineerWe are seeking a highly skilled Senior Design For Testability (DFT) Engineer to drive the development and implementation of DFT strategies for complex SoC/ASIC designs. As a key member of our engineering team, you will be responsible for leading the design and verification of DFT features, collaborating with cross-functional teams, and ensuring world-class testability and manufacturability of silicon products.Key Responsibilities:Develop and implement DFT architectures, planning, and implementation for complex SoC/ASIC designs.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Develop and maintain DFT automation scripts and infrastructure.Requirements:Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.Strong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Nice to Have:• Strong leadership, team collaboration, and communication skills.• Deep understanding of silicon test challenges and test coverage improvement.Note: The job description is subject to change based on business needs.

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