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Lead Digital Fault Tolerance Engineer

2 weeks ago


bharatpur, India beBeeFaultTolerance Full time

About the Role:We are seeking a seasoned expert in Digital Fault Tolerance (DFT) to lead our efforts in planning, insertion, verification, and closure of Pattern-Based Built-In Self-Test (PMBIST).The ideal candidate will be responsible for running end-to-end DFT flows with minimal supervision, debugging patterns, and driving coverage targets.PMBIST Architecture, Integration, and VerificationAtmospheric Post-Pattern Generation (ATPG)Fault ModelsScan InsertionPattern DebuggingCoverage Analysis and Sign-offSkill Requirements:Familiarity with Synopsys, Mentor, or Cadence DFT tools is essential. Experience working on complex System-on-Chip (SoC) designs is highly desirable.