IC Layout Engineer

1 week ago

bangalore, India L&T Semiconductor Technologies Full time

L&T Semiconductor Technologies (LTSCT), a fully owned subsidiary of L&T, is the first major Indian Semiconductor product company - a fabless company for designing & delivering Smart Devices for Global Customers. A company that provides Semiconductor Devices and Technology partnerships by helping customers realise energy efficient, high-performance systems to benefit from data, electrification and software defined technology trends.

Our aim is to build an India-based semiconductor portfolio of Smart Devices across MEMS Sensors, Power, Analog Mixed Signal & RF products, to support Automotive, Industrial, Energy and Telecommunication verticals.

We have a presence in four prominent geographies i.e. US, Europe, Japan and India, with offices in Austin, Munich, London, Tokyo, Bangalore and Chennai.


About the Role:

IC Layout Engineer

Responsible for design, planning, scheduling and execution of Full Chip development with analog and digital components


Responsibilities:

  • Responsible for design, planning, scheduling and execution of Full Chip development with analog and digital components.
  • Perform Full chip feasibility and die size estimation in core limited and pad limited approach for different bonding schemes.
  • Expertise with top to bottom and bottom to top approach floorplan, power schemes, Interface signal planning and routing, physical verification and quality check.
  • Make sure to deliver quality full chip layout on-schedule meeting design intent - Speed, Capacitance, Resistance, Power, Noise and Area.
  • Works on complex issues and exercises judgement in selecting methods for obtaining results.
  • Builds strong business relationships with cross-functional teams for smoother execution of projects.
  • Work closely with Synaptic Global Analog and Digital Design and CAD engineering teams.



Required Skills:

  • Bachelor's or master’s in electrical engineering or ECE or EEE.
  • 8+ years relevant experience in Custom Analog Layout design and development.


Preferred Skills:

  • Good understanding of active and passive devices, circuits and electrical fundamentals.
  • Expert of CMOS, FDSOI and FinFET fabrication concepts, Deep Nwell and triple well process.
  • Expert of analog layout techniques, electromigration, ESD, latch up, crosstalk, shielding and deep sub-micron challenges.
  • Expertise with SOC and ASIC design flows, procedures and deliverables.
  • Hands-on experience with Virtuoso L/XL/GXL (6.1.x and 12.1.x), Calibre, PERC, STARRC, Totem and ESRA tools.
  • Strong analytical, debug and problem-solving skills in resolving layout design challenges and physical verification issues.
  • Flexible to work in a cross functional and multi-site team environment, spanning different time zones.
  • Must have good verbal and written communication skills.

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