Senior Digital Fault Tolerance Architect

7 days ago


rajkot, India beBeeDft Full time

Job OpportunityWe are seeking an exceptional DFT Architect to spearhead the development of cutting-edge SoC/ASIC designs. As a key member of our team, you will be responsible for creating innovative DFT strategies, mentoring junior engineers, and collaborating with cross-functional teams to deliver world-class testability and manufacturability.About the RoleDevelop and drive DFT architecture for multiple complex projects.Lead the implementation and verification of DFT features including scan insertion, compression, ATPG pattern generation, MBIST, boundary scan, and IJTAG.Manage the end-to-end DFT flow from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.RequirementsB.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.7+ years of experience in DFT for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as Synopsys, Siemens EDA, and Cadence.Strong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Preferred QualificationsExperience with hierarchical DFT and low-power DFT methodologies (UPF).Exposure to post-silicon validation and failure analysis.Familiarity with safety-critical designs (ISO 26262) and functional safety.What We OfferA challenging role in driving high-performance SoC/ASIC designs.The opportunity to collaborate with top-tier engineers and global semiconductor leaders.Competitive compensation and fast-track growth opportunities.This is a fantastic chance to join our dynamic team and contribute to the development of innovative technologies.



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