Senior Digital Fault Tolerance Specialist

2 weeks ago

tiruppur, India beBeeDFT Full time

We are seeking a Technical Lead for Digital Fault Tolerance to oversee the development of complex SoC/ASIC designs.This role involves defining and implementing digital fault tolerance strategies, as well as collaborating with cross-functional teams to ensure world-class testability and manufacturability of silicon products.Define and drive digital fault tolerance strategy and architecture for multiple ASIC/SoC projects.Lead implementation and verification of digital fault tolerance features such as scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan (IEEE 1149.1/1149.6), IJTAG (1687).Manage end-to-end digital fault tolerance flow from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.Perform pattern generation, fault simulation, and debug test coverage gaps.Own digital fault tolerance signoff, timing closure (digital fault tolerance-related paths), and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE, and yield optimization.Mentor and guide junior engineers, conduct design reviews and training sessions.RequirementsB.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.7+ years of experience in digital fault tolerance for complex ASIC or SoC designs.Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.Strong knowledge of RTL design, STA, and synthesis flows.Proficient in scripting languages (Python, Perl, Tcl) for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration, and communication skills.

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