Senior/Lead STA engineer
7 hours ago
We're Hiring: STA Engineer | 5–15 Years Experience | Bangalore Company: ACL Digital Company Location: Bangalore Experience: 5 to 15 Years Job Type: Full-Time ACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs. If you're an STA expert who thrives in fast-paced, technically challenging environments, we want to hear from you Responsibilities: • Own and drive timing closure for complex SoC and ASIC designs across multiple technology nodes • Perform full-chip and block-level timing analysis using industry-standard tools (Primetime, Tempus, etc.) • Collaborate with RTL, synthesis, physical design, and verification teams to resolve timing violations • Develop and maintain timing constraints (SDC), run STA checks (setup, hold, DRV, SI), and support ECO timing closure • Contribute to methodology improvements and timing signoff strategies • Report timing status, risks, and closure plans to technical leads and project stakeholders Required Skills & Experience: • 5–15 years of solid hands-on experience in STA and timing closure • Strong expertise in timing concepts, constraints development, and signoff methodology • Proficient in tools like Synopsys Primetime, Cadence Tempus • Solid understanding of clock tree design, DFT, multi-mode multi-corner (MMMC) analysis • Good scripting skills (TCL/Perl/Python) to automate and debug flows • Experience with advanced nodes (7nm/5nm/FinFET) is a plus • Strong analytical, problem-solving, and communication skills Why Join Wafer Space? • Be part of a high-growth, innovation-driven semiconductor company • Work on state-of-the-art technologies with leading global clients • Collaborative and empowering work culture • Competitive compensation and flexible work options • Opportunity to grow your career in a technically challenging environment Interested? Send your resume to
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Senior/Lead STA engineer
7 days ago
bangalore, India ACL Digital Full timeWe're Hiring: STA Engineer | 5–15 Years Experience | BangaloreCompany: ACL Digital CompanyLocation: BangaloreExperience: 5 to 15 YearsJob Type: Full-TimeACL Digital is looking for Senior Static Timing Analysis (STA) Engineers with solid experience in timing closure of advanced SoC designs.If you're an STA expert who thrives in fast-paced, technically...
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STA Lead
1 week ago
Bangalore, India Mulya Technologies Full timeLarge Semiconductor Service Organization with revenue over 600 Million USD Location: Bangalore STA Lead Experience : 7+ Years Work location : Bangalore Well versed with the timing closure (STA), timing closure methodologies. Pre/Post-layout constraint development to timing closure. Handshake with the design team and develop functional/DFT constraints. IP...
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STA Lead
1 week ago
bangalore, India Mulya Technologies Full timeLarge Semiconductor Service Organization with revenue over 600 Million USDLocation: BangaloreSTA LeadExperience : 7+ YearsWork location : BangaloreWell versed with the timing closure (STA), timing closure methodologies.Pre/Post-layout constraint development to timing closure.Handshake with the design team and develop functional/DFT constraints.IP level...
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STA Engineer
4 hours ago
bangalore, India Mirafra Technologies Full timeSTA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | BangaloreWe are looking for skilled STA / PTPX Engineers with strong experience in timing sign-off and power analysis. Key Skills:• STA sign-off, MCMM timing closure• PrimeTime / PrimeTime-SI / PrimeTime-PX• PTPX power analysis (dynamic & static)• Timing constraints, ECOs,...
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STA Lead
1 week ago
bangalore, India Mulya Technologies Full timeLarge Semiconductor Service Organization with revenue over 600 Million USDLocation: BangaloreSTA LeadExperience : 7+ YearsWork location : Bangalore- Well versed with the timing closure (STA), timing closure methodologies.- Pre/Post-layout constraint development to timing closure.- Handshake with the design team and develop functional/DFT constraints.- IP...
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STA Engineer
7 days ago
bangalore, India Mirafra Technologies Full timeSTA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | BangaloreWe are looking for skilled STA / PTPX Engineers with strong experience in timing sign-off and power analysis. Key Skills:• STA sign-off, MCMM timing closure• PrimeTime / PrimeTime-SI / PrimeTime-PX• PTPX power analysis (dynamic & static)• Timing constraints, ECOs,...
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STA Engineer
7 days ago
Bangalore, India Mirafra Technologies Full timeSTA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | Bangalore We are looking for skilled STA / PTPX Engineers with strong experience in timing sign-off and power analysis. 🛠️ Key Skills: • STA sign-off, MCMM timing closure • PrimeTime / PrimeTime-SI / PrimeTime-PX • PTPX power analysis (dynamic & static) • Timing constraints,...
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STA Engineer
7 days ago
bangalore, India Mirafra Technologies Full timeSTA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | Bangalore We are looking for skilled STA / PTPX Engineers with strong experience in timing sign-off and power analysis.🛠️ Key Skills: • STA sign-off, MCMM timing closure • PrimeTime / PrimeTime-SI / PrimeTime-PX • PTPX power analysis (dynamic & static) • Timing constraints,...
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Full Chip STA Lead
2 weeks ago
bangalore, India eInfochips (An Arrow Company) Full timeFull Chip STA Lead (8+ Years Experience) Locations: Bangalore, Hyderabad, Noida, Ahmedabad, Chennai, Pune Job Description: We are looking for an experienced Full Chip STA Lead with strong expertise in full-chip timing, constraint management, and cross-functional collaboration. The ideal candidate will drive timing closure activities for complex SoCs and...
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Full Chip STA Lead
4 hours ago
bangalore, India eInfochips (An Arrow Company) Full timeFull Chip STA Lead (8+ Years Experience) Locations: Bangalore, Hyderabad, Noida, Ahmedabad, Chennai, Pune Job Description: We are looking for an experienced Full Chip STA Lead with strong expertise in full-chip timing, constraint management, and cross-functional collaboration. The ideal candidate will drive timing closure activities for complex SoCs and...
