Senior Timing Closure Specialist

1 week ago

visakhapatnam, India beBeeTimingClosureExpert Full time

Timing Closure ExpertWe are seeking an experienced professional to drive timing closure activities for complex SoCs and provide technical guidance to junior engineers.Functional and test constraints must be handled at block and top levels.Static timing analysis (STA) must be performed for block-level and full-chip sign-off.The incumbent will own ECO generation at the top level and coordinate with block owners for timing/functional ECO implementation.A close working relationship with synthesis teams is required for block-level and top-level synthesis.Automation initiatives using Perl, Tcl, Awk, or Python will be driven by the successful candidate.Junior engineers will be mentored and guided on technical aspects.About the RoleThis role requires a strong understanding of STA principles and their application in the development of complex ICs.RequirementsExperience in static timing analysis and constraint handling.Strong knowledge of Verilog and VHDL.Ability to work effectively in a team environment.Excellent communication and problem-solving skills.Proficiency in one or more programming languages such as Perl, Tcl, Awk, or Python.What We OfferAs a Timing Closure Expert, you will have the opportunity to work on exciting projects and contribute to the development of complex ICs. We offer a competitive salary and benefits package, as well as opportunities for professional growth and development.How to ApplyIf you are a motivated and experienced professional looking for a new challenge, please submit your resume and cover letter for consideration.

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