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Silicon Test Architect
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Senior Test ArchitectAs a key member of our engineering team, you will be responsible for leading the development and implementation of complex test architectures for SoC/ASIC designs. This is an exciting opportunity to work with cross-functional teams to drive innovation in digital design.Define and implement comprehensive test strategies to ensure world-class quality and reliability of silicon products.Develop and maintain automated test scripts and infrastructure to streamline end-to-end testing flow.Collaborate closely with RTL, STA, PD, and test engineering teams to ensure seamless integration and optimize overall system performance.Design and deliver efficient test solutions that meet or exceed customer requirements.Lead test design reviews and training sessions to mentor junior engineers.Key Responsibilities:Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.Implement and verify DFT features like scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan (IEEE 1149.1/1149.6), IJTAG (1687).Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up.Requirements:Strong expertise in digital test and verification methodologies.Proven experience with DFT tools and scripting languages (e.g., EDT, Python).Excellent communication and collaboration skills.Ability to lead and motivate cross-functional teams.Knowledge of semiconductor manufacturing processes and ATE systems.
