Senior DFT Engineer Position

2 days ago

dombivli, India beBeeDftLeader Full time

Job OverviewWe are seeking a seasoned expert to lead our DFT architecture, planning and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams and ensure world-class testability and manufacturability of silicon products.Key Responsibilities:Define and drive DFT strategy and architecture for multiple ASIC/SOC projects.Lead the implementation and verification of DFT features such as scan insertion and compression, ATPG pattern generation and fault grading, MBIST and Logic BIST insertion and validation, boundary scan (IEEE 1149.1/1149.6), IJTAG (1687).Manage end-to-end DFT flow from RTL to gate-level netlist and silicon bring-up.Collaborate with RTL, STA, PD and test engineering teams for seamless integration.Perform pattern generation, fault simulation and debug test coverage gaps.Own DFT signoff, timing closure and ATE pattern delivery.Support silicon bring-up, test vector validation on ATE and yield optimization.Mentor and guide junior DFT engineers, conduct design reviews and training sessions.Develop and maintain DFT automation scripts and infrastructure.Requirements:Bachelor's or Master's degree in Electronics, Electrical or VLSI Design.At least 7 years of experience in DFT for complex ASIC or SOC designs.Expertise in scan insertion, compression, ATPG, MBIST and boundary scan.Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.Strong knowledge of RTL design, STA and synthesis flows.Proficient in scripting languages for flow automation.Deep understanding of silicon test challenges and test coverage improvement.Strong leadership, team collaboration and communication skills.Preferred Qualifications:Experience with hierarchical DFT and low-power DFT methodologies.Exposure to post-silicon validation and failure analysis.Familiarity with safety-critical designs and functional safety.Experience working in advanced nodes.Why Choose Us?Opportunity to lead DFT for high-performance next-gen SoCs and ASICs.Collaborate with top-tier engineers and global semiconductor leaders.Competitive salary and fast-track growth opportunities.

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