Senior Staff Engineer
2 months ago
Client of Connectpro
RTL micro architecture design /integration for IoT SoCs
· Integration of sub-systems/IPs while considering sub-system/IP features/configurations/generics, power/clock/reset, standard/proprietary interface requirements.
· Work with digital/analog/RF IP teams to arrive IP configuration at SoC level .
· Drive power topology, clock structure and reset strategy at SoC level.
· Identify low power opportunities at IP/SoC level.
· Arrive IO requirements/muxing .
· SoC infrastructure IP (like power, reset, clocking) micro architecture, development.
· Run and analysis of RTL quality checks like LINT and CDC .
· Active participation while defining power intent of SoC.
· Active contribution for synthesis constraints at SoC level.
· Participate, as applicable, silicon debug activities.
· Help, drive improvements on-the-fly in all the above areas (as project executes).
· Ensure an inclusive teamwork environment, inspire team members, and role model.
· Work effectively with several stakeholder teams locally/globally.
You are best equipped for this task if you have:
· B Tech with 7+ years of experience or M Tech with 5+ year of experience in IP Design with few years of experience of SoC design.
· Must have several years of experience of ASIC design flow and mentoring junior engineers.
· Must have expertise on processor based SoC design which includes (but not limited to), ARM processor, DMAs, power/clock/reset controllers, interfaces like USB/SDIO/PCIe/SPI/UART .
· Must have good understanding of high-speed interfaces like USB, SDIO, PCIe and proven track record in such developments.
· Expertise in System Verilog/VHDL languages.
· Expertise with scripting.
· Team player with good communication skills.
· Strong analytical and problem-solving skills.
· Familiarity with Security architecture/requirements is a plus.
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