Senior Design Manager

3 weeks ago

Bengaluru, India L&T Semiconductor Technologies Full time

Role- Sr. Design Manager- SoC Verification
Stream - R&D
Reporting To - Chief Development Officer / Global Head of Engineering
Location - Bengaluru

COMPANY DESCRIPTION:

L&T Semiconductor Technologies (LTSCT), a fully owned subsidiary of L&T, is the first major Indian Semiconductor product company - a fabless company for designing & delivering Smart Devices for Global Customers. A company that provides Semiconductor Devices and Technology partnerships by helping customers realise energy efficient, high-performance systems to benefit from data, electrification and software defined technology trends.

Harnessing the engineering mastery of L&T, LTSCT is forging a path to a world-class semiconductor ecosystem rooted in India. We aim to rewrite the rules of cutting-edge technology through relentless innovation to foster a vibrant culture of ingenuity, fuelling progress on every chip.

We have a presence in four prominent geographies i.e. US, Europe, Japan and India, with offices in Austin, Munich, London, Tokyo, Bangalore and Chennai.

JOB DESCRIPTION:

LTSCT’s Chief Development Organization and Global Engineering team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for LTSCT‘s Automotive, Industrial, Energy and Telecom infra business lines. The team is challenged to produce industry leading solutions covering very cost sensitive, low power devices to highly integrated, high performance, multidomain devices compliant with the latest automotive and industrial safety and security standards.

AREAS OF RESPONSIBILITY:

Lead SoC RTL and Verification R&D team driving technical execution and best in class methodologies used in the design of advanced microcontrollers and microprocessors.
In this role you will also lead SoC Verification team, including training and mentoring NCG’s and developing next level verification leads
Fully own RTL delivery for a multitude of projects
Responsible for developing team members goals and development plans ensuring a high performing SoC verification team.
Work closely with system architects to define high level specifications that are implementable and robust.
Interface with verification/validation teams to ensure design quality and robustness.
Work with various EDA vendors to deploy next generation tools
Build strong collaboration with other R&D teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones
Strong Knowledge of protocols such as Ethernet/802.3, PCIe, MIPI, PHY IPs, etc , AMBA, CHI, ACE, AXI bus protocols , VHDL/Verilog/System Verilog, OVM/UVM, Class-based verification methodologies
Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence overall design improvements and verification methodologies
Complete ownership for SoC verification quality sign-offs ensuring all deliverables for team hand-offs.
Drive best in class verification methodologies collaborating with global internal and external SME’s and developing adoption and compliance processes. Including, driving key innovation strategies which significantly impact efficiency and quality for overall R&D and ROI

QUALIFICATIONS:

Degree in Electrical Engineering or Computer Science, with minimum 15 years of experience on IP/Sub-System Verification. Masters degree in the area of computer or electrical engineering from a reputed university will be an added advantage
Candidate should be an experienced manager with a history of leading successful SoC RTL and Verification teams.
Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.
Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency.
Advanced knowledge of Verilog, System Verilog, C/C++, Shell.
Good knowledge in scripting like Perl, TCL or Python is a plus
Good knowledge of formal verification methodologies and assertions.
Experience with debugging of designs pre- and post-silicon, in simulation and on the bench.
Excellent written and verbal communication skill.
Experience with System Verilog and front-end tooling (simulation, waveform viewers, lint, CDC, RDC, etc.) is required, as well as highly efficient FE methodologies.
Must have worked on complex, multi-core SoC’s with extensive interconnects and a large range of peripherals.

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