Tech Lead, Fpga Design
1 month ago
INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and solutions with a unique value proposition for 5G applications. To learn more about InnoPhase, visit www.innophaseinc.com.
InnoPhase and Synergic Emergence have a co-employment relationship. For over three years, InnoPhase has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and InnoPhase will provide employment, evaluation, and advancement. By outsourcing some HR functions, InnoPhase can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products.
Job Description
Tech Lead, FPGA Design & Verification: You will be working with a team of design engineers to develop FPGA and novel SoC products for connectivity and communications. You will also be a key contributor to product definition and resulting detailed device performance and functional requirements specifications. In addition to delivering high quality digital solutions in the context of the product architecture, the team supports other disciplines with work product such as Verilog stimulus files, test benches for device bring up/characterization, test vectors for product manufacturing, etc.
Key Responsibilities
Develop multiplatform FPGA designs for InnoPhase emulation platforms and also Cellular reference product solutions.
Develop FPGA design specifications, communicate and verify these specifications with the RF/FW designers.
Debug designs and provide timely closure.
Perform Synthesis, P&R and generated FPGA images.
Bring up emulation platform with SW and system teams.
Develop and own functional blocks to be used on multiple platforms.
Hands on debug capability using lab equipment and JTAG.
Contribute to/review SoC specifications and architectures.
Front to back digital design and verification – RTL through physical implementation.
Hands on technical leadership.
Help define and socialize digital/system design, implementation methodologies and test strategies and flows.
Job Requirements
M.Tech/PhD EE/CS preferred.
10++ years of working with FPGA architecture, implementation, and verification.
Experience with Xilinx & LOGIC Synthesis tools such as VIVADO.
Experience w/ embedded ARM core and bus sub-system integration in XILINX Development boards such as ZCU102.
Experience with Peta Linux build for FPGA ARM SOC applications.
Experience in creating Sanity testbench and RTL block integration.
Experience with Xilinx, TCL, SVN/GIT.
Experience with embedded systems, wireless protocols, power management, signal processing and standard digital interfaces.
Deep RTL design knowledge (Verilog/VHDL) and System Verilog.
Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers).
Proven knowledge of synthesis, static timing, F2B digital SoC design flow.
Knowledge of languages such as C/C++, Perl, Tcl and Python.
Strong communication and presentation skills.
Good skills and interest in mentorship.
Ability to foresee issues and design in flexibility and workarounds for both known and unknown unknowns.
Team player with strong sense of urgency to complete projects on time.
Desirable Skills
Experience with Xilinx Development Toos/Flow.
Experience lab debugging tools such as JTAG, logic analyzer.
Able to work effectively with incomplete or changing requirements.
Good skills an interest in mentorship.
Strong knowledge of mixed signal concepts.
Focused, goal driven finisher.
Benefits
Competitive salary and stock options.
Learning and development opportunities.
Employer paid health Insurance.
Casual, Sick & parental leaves.
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