Power Convergence Lead Physical Design

Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career. Overview WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities Physical Design (Low Power) Technologist THE ROLE: As a member of the Strategic Silicon Solution Group Full Chip Physical Design team, you will help bring to life cutting-edge designs.You will work closely with the Full Chip/Subsystem Floorplan / Netlist, Tile/Block/Partition level Physical Design, Full Chip Static Timing Analysis and Constraints teams, to achieve first pass silicon success. THE PERSON: - This person will be working on Full chip / Sub-system level Physical Design, Timing Analysis, Synthesis, Logical equivalence, Physical Verification, Power design/implementation/signoff, and will act as a mentor/coach/guide to Design Engineers. Will work very closely with Fellows, Principal Engineers, Architects, Technology/CAD teams and collaborate with cross functional worldwide teams. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills. Should have hands on Physical Design experience and must have handled RTL to GDS II at Top level or Hierarchical top level for at least few tape outs. Must have led physical design team/s in the capacity of technical lead or as a go to person. KEY RESPONSIBILITIES: - Oversee and manage power convergence and sign-off procedures across various SOC classes. - Evaluate and approve power metrics for SOCs across diverse use cases. - Establish comprehensive power analysis plans and collaborate closely with the physical implementation team throughout the project lifecycle to ensure low power implementation and optimization. - Conduct RTL power estimation and work together with RTL designers to enhance overall power efficiency. - Undertake low power design initiatives that include power estimation, addressing annotation issues, and employing optimization techniques like clock gating, power gating, power switch implementation, and other methods to reduce total power consumption. - Execute RTL to GDSII design implementation and troubleshoot flow at both chip-level and module-level. - Achieve PPA (Power, Performance, Area, and Schedule) closure and develop processes for essential IPs like CPUs, Graphics, Multimedia, Fabric cores, and other significant subsystems. - Implement clock tree synthesis and advanced clock tree techniques at the full chip or subsystem level. - Possess hands-on experience with reference flows and exhibit strong debugging skills. - Maintain and update technology-related collateral. - Bring experience with technologies at 5nm and below. PREFERRED EXPERIENCE: - 10-15 years of relevant work experience. - Expertise in ICC2/ FC (Fusion Compiler) and/or Innovus - Physical Design flows/methodologies or equivalent tools. - Expertise in Signoff tools like Primetime for Timing, Ansys Redhawk on EMIR, PT-PX for Power signoff - Should have worked as a go-to person or technical lead for at least a few full chip projects. - Strong technical leadership and ability to mentor/guide/coach design engineers to achieve and deliver project goals. - Strong inter-personal skills and ability to collaborate with teams spread across multiple geos. - Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts. ACADEMIC CREDENTIALS: - Bachelor's or Master's degree in Computer/Electronics/Electrical Engineering #LI-SR4 Benefits offered are described: . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.