Sr. Performance Verification Engineer

Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career. SENIOR SILICON PERFORMANCE VERIFICATION ENGINEER THE ROLE: The successful candidate will join AMD's Computing and Graphics Performance Verification team. The team's mandate is to analyze AMD's next generation SOC architecture and performance through modeling and RTL simulation. This role will involve working with SOC and IP architects to evaluate and improve performance and collaborating with design and verification teams to execute performance verification plans. THE PERSON: The ideal candidate has a passion for modern, complex processor architecture, performance, digital design, and verification. The candidate must have excellent communication skills and experience working with teams in different sites and time zones. The candidate must have strong analytical and problem-solving skills, be willing to learn, and be ready to take on new challenges. KEY RESPONSIBILITIES: - Work in the Computing and Graphics Performance Verification team - Develop simulation infrastructure and methodology advances that are required to model specific customer requirements - Work with architects and designers to debug functional and performance issues - Develop, track, and communicate project plans internally and with AMD customers - Utilize customer feedback to improve performance testing and enhance deliverables - Contribute to a global team that will execute to a high standard of quality - Engage in multi-discipline interactions with IP and SoC architect and verification teams, SW/FW developers, tool owners, logic designers, and verification engineers - Identify, resolve, and document architectural performance issues PREFERRED EXPERIENCE: - 3-5 years of professional experience in the industry with a proven track record of successfully building and delivering complex SOC computing devices - Experience with computer system simulation and performance evaluation - Experience with ASIC hardware design and verification languages/tools (Verilog, System Verilog, System C, UVM/UVC) - Proficiency in debugging RTL code using simulation tools - Proficiency with programming and scripting languages (C/C++, Perl, Python, etc.) - Experience analyzing system bottlenecks and optimizing computing systems for performance - Detailed microarchitecture knowledge in one or more of the following: CPU, GPU, DSP, NPU, multimedia co-processor, I/O subsystem, DRAM controller ACADEMIC CREDENTIALS: Bachelors degree in Computer Engineering/Electrical Engineering plus 5 years full-time experience in IP hardware design, or Masters degree plus 3 years experience in same. #LI-MK1 Benefits offered are described: . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.