[Only 24h Left] Lead Engineer

1 week ago

Bengaluru, India Tessolve Full time

ob Title: Physical Design Lead Location: [Insert Location] Department: Engineering / ASIC Design Experience: 5+ years in physical design Key Responsibilities: Required Qualifications & Skills - Bachelor’s or Master’s degree in ECE/Electronics/EEE or related field. - 3 + years of physical design / back-end implementation experience (block-level or SoC) in VLSI. - Proven experience in floor-planning, placement, CTS, routing, timing closure, sign-off physical verification (DRC/LVS/antenna). - Hands-on with EDA tools: Synopsys, Cadence, Mentor (specifically tools like ICC2, Fusion Compiler, Innovus, PrimeTime, Tempus). - Strong understanding of timing closure concepts: setup/hold violations, timing paths, PVT corners, multi-mode multi-corner. - Good knowledge of power, area, performance trade-offs; power-optimization techniques. - Good scripting knowledge (Tcl, Perl, Python) for automation of PD flows. - Ability to analyze and debug physical design issues such as congestion, IR-drop, EM, signal integrity, crosstalk. - Excellent communication skills and ability to work in cross-functional teams. Key Responsibilities - Execute block-level / subsystem or full-chip physical implementation flow: floor-planning, power-planning, placement, clock-tree-synthesis (CTS), routing, optimization. - Work on timing closure: static timing analysis (STA), timing-driven placement & routing, working across PVT corners, on-chip variation, multi-corner multi-mode (MCMM). - Perform physical verification sign-off: DRC, LVS, antenna, ERC checks; ensure full compliance for GDSII hand-off. tessolve.com - Handle power integrity, signal integrity, IR-drop, electromigration (EM) issues, and noise/crosstalk mitigation. - Work with low-power design techniques: power gating, multi-voltage domains, clock gating. - Use industry-standard EDA tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, Mentor Olympus, PrimeTime/Tempus) and scripting (Tcl, Perl, Python) for automation. Foundit+1 - Collaborate with front-end, DFT, verification, package teams for design convergence, timing/area/power trade-offs. - Debug physical implementation issues (placement congestion, routing bottlenecks, timing violations, DRC/LVS failures) and propose solutions. - Participate in sign-off flows, tape-out readiness, hand-off to foundry/assembly/test teams. - Maintain documentation (floor-plan, power-plan, partitioning reports, sign-off checklists) and contribute to PD methodology/flow improvements.

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