Ams Io Expert

Purpose: We are seeking a highly skilled and motivated IO Design Expert with deep experience in designing GPIOs, specialty analog/digital IOs, and ESD protection circuits across technology platforms ranging from BCD technologies (e.G., 180nm/130nm/55nm) to advanced CMOS nodes (e.G., 28nm, 16nm, 12nm, 7nm, 5nm). You will play a critical role in the architecture, schematic design, layout oversight, simulation, verification, and qualification of IO libraries for complex SoCs with stringent reliability and performance requirements. Areas Of Responsibility: Architect and design a wide range of IO cells: - General Purpose IOs (GPIOs) - High-Speed IOs (LVDS, CML, SSTL, HSTL, etc.) - Power IOs (e.G., VDD, VSS pads) - Analog IOs for sensor interfaces, ADC/DAC connections - ESD protection devices and clamps (CDM, HBM, MM compliance) - High-voltage tolerant IOs (for BCD technologies) - Collaborate with system architects and package designers to define pad ring structure, signal assignments, and power integrity constraints. - Lead IO library development, including reusable IP blocks across multiple SoCs and technology platforms. - Perform corner simulations (PVT, aging, mismatch) and electrostatic discharge simulations to ensure design robustness. - Validate designs through post-layout verification, LVS/DRC, and EM/IR checks. - Work with layout engineers to guide physical design and ensure DFM compliance. - Interface with foundries for tapeout, IP sign-off, and PDK updates. - Lead silicon characterization, correlation with simulations, and root-cause analysis for silicon issues. - Ensure compliance with automotive (AEC-Q100), industrial, and consumer qualification requirements when applicable. Experience and Qualification: - Master’s/Bachelor’s degree in Electrical Engineering, Microelectronics, or related field. - 10+ years of experience in custom analog/mixed-signal IO design. - Proven track record of IO designs in BCD (e.G., 180nm, 130nm) and advanced FinFET/SOI nodes (e.G., 28nm, 16nm, 7nm). - Strong understanding of: - ESD design techniques - Latch-up prevention - IO reliability (TDDB, HCI, NBTI) - Signal and power integrity in IO domains - Packaging parasitics and bondpad modeling - Proficiency in Cadence Virtuoso, Spectre, Calibre, HSPICE, or equivalent tools. - Deep experience with foundry PDKs, DRC/LVS, and analog layout best practices. - Familiarity with automotive-grade and industrial-grade design requirements. Excellent problem-solving, communication, and documentation skills. Technical And Behavioural Skills: - Strong written and verbal communication skills. Proactive, collaborative, and creative approach to innovation, technical development and consensus facilitation to influence optimal project results. Strong team player. - Staying updated with the latest IO Design techniques, standards, and tools. - Self-Motivated; Team player; Fast Learner; Analytical - Having patents on names and papers in IEEE journals will be greatly appreciated - Excellent problem-solving, analytical, and communication skills. - Ability to work effectively in a collaborative team environment. - Experience with multi-voltage IOs, level shifters, or high-speed SERDES IO interface support. - Exposure to chip-level ESD strategy and pad ring co-design with digital place-and-route teams. - Knowledge of chip-package-board co-design and related modeling techniques. - Familiarity with IP qualification documentation (e.G., IO validation reports, ESD/EMC results, corner simulation logs, etc.). Qualifiers for the Role / Necessary Experience and Skills Required for the Role: - Bachelor’s/Masters/PhD degree in engineering in Electronics and Electrical Engineering with excellent academic records.