Sr. CPU Subsystem Manager/Director

Job Description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Role Overview

We are looking for an experienced CPU Subsystem Manager/ Director to lead the pre-silicon RTL and verification of high-performance CPU microarchitectures designed for AI/ML applications. This role demands a deep expertise in computer architecture, microarchitecture, design, and verification, coupled with strong leadership skills to drive a team toward high-quality execution.

Responsibilities

- Lead and mentor a team of engineers in RTL design and verification for the CPU Subsystem.
- Define and manage the subsystem IP roadmap, covering microarchitecture, design, and verification, while planning resources for CPUs used across multiple product lines.
- Work closely with RTL, Physical Design, and CPU Performance teams to align design and verification efforts for seamless integration.
- Develop Universal Verification Components (UVCs) from scratch and implement test plans for CPU subsystem validation.
- Conduct functional verification at the RTL level, ensuring comprehensive coverage and continuous improvement.
- Utilize C++, scripting languages, and industry-leading simulation tools to verify complex CPU architectures.
- Collaborate with Architecture, Design, and Software teams to define and negotiate program objectives while guiding the verification team through planning, execution, and project closure.
- Ensure adherence to quality metrics and best practices in microprocessor verification.
- Drive team development by setting individual and collective goals aligned with organizational vision.

Experience & Qualifications

- Bachelors, Masters, or PhD in Electrical Engineering, Computer Science, or related fields.
- Proven leadership experience managing design and verification teams across complex IP development at unit, subsystem, or top levels.
- Expertise in SystemVerilog, UVM, and verification methodologies, with hands-on experience in testbench development and coverage-driven verification.
- Strong knowledge of computer architecture, microprocessor verification, cache systems, and interconnects (NOC, AXI, CHI, etc.).
- Experience with DFD IP verification is a plus.
- Excellent strategic planning, communication, and cross-functional collaboration skills.
- Ability to drive technical strategy, influence organizational goals, and align teams for execution.

This role offers an exciting opportunity to contribute to cutting-edge CPU designs in a fast-paced, innovative environment.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.

As this position will have direct and/or indirect access to information, systems, or technologies that are subject toU.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee informationand supporting documentation will be required and considered as a condition of employment.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

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