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Technical Lead physical design Urgent Search

4 weeks ago

Bengaluru, Karnataka, India HCLTech Full time
About HCL:

HCLTech offers end-to-end semiconductor services across the entire chip lifecycle

- Design Services: RTL design, microarchitecture, verification, and tape-out.
- Package Design: Substrate layout, bonding diagrams, and routability analysis.
- Test & Validation: Memory BIST, wafer sort, probe card design, pre/post-silicon validation.
- Qualification & Manufacturing: HTOL, UHAST, burn-in boards, prototype and volume production.
- Fab Services: Automation, reliability testing, failure analysis, and refurbishments.
- Software & Electrical Engineering: Control systems, power electronics, DevOps, and simulator development.
- AI & GenAI Accelerators: AI-assisted chip design, test code generation using GPT-4, and digital twin solutions for fab optimization.

- 25+ years in semiconductor engineering.
- 4,500+ engineers working with top 13 global OEMs.
- 200+ tapeouts across major foundries like Intel, Samsung, TSMC, and GlobalFoundries
- Expansion in Brazil, Vietnam, Netherlands, Japan, and India (Bengaluru) to meet global demand

Experience: 7 - 15+ yrs

Location: Bangalore/ Noida/ Chennai/ Kochi

Notice period: immediate to 90 days.

Role Overview:

The Physical Design Lead is responsible for driving the physical implementation of complex integrated circuits (ICs) from RTL to GDSII. This role involves leading a team of engineers, defining design strategies, and ensuring that performance, power, and area targets are met. The position requires deep expertise in physical design flows, EDA tools, and semiconductor technologies.

Required Qualifications:

- 7+ years of experience in physical design, with at least 2–3 years in a lead role.
- Expertise in EDA tools such as Cadence, Synopsys, or Mentor Graphics.
- Strong knowledge of RTL-to-GDSII flow, timing closure, and power analysis.

Preferred Skills:

- Experience with advanced nodes (7nm, 5nm, or below).
- Proficiency in scripting languages (Tcl, Python, Perl).
- Familiarity with Design for Manufacturability (DFM) and Design for Test (DFT).
- Understanding of statistical timing analysis and parasitic extraction.