
▷ Apply Now: Staff Engineer Verification
7 days ago
Job Description
Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices.
Job Description
In your new role you will:
- Be part of a verification team utilizing leading-edge verification tools and methodologies to enable the functional verification of large, and complex memory devices.
- Responsible for:
- Designing self-checking test benches using modern verification techniques
- Implementing functional coverage and assertions using System Verilog and UVM.
- Developing TB environment using SV and UVM.
- Developing test and functional coverage plans based on device specifications.
- Analyzing and debugging simulation failures, as well as analyzing functional coverage results to guarantee zero defect outcomes.
Your Profile
You are best equipped for this task if you have:
- Engineering in Electrical/electronic streams , or equivalent experience.
- 5+ years experience in constrained-random, coverage driven verification environments.
- Experience in RAL
- Experience in developing the test bench from scratch using System Verilog (SV) HDVL and UVM (Universal Verification Methodology).
- Expertise in Gate Level simulations (GLS) and have debugged, root caused real netlist issues.
- A solid understanding of verification concepts and experience designing class-based test benches.
- C coding, Formal verification methods and Power aware simulation will be an advantage
- Excellent written and oral communication skills
- Strong debugging skills, functional simulations and GLS simulations.
Contact:
[Confidential Information], LinkedIn
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Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.
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