
FPGA RTL Design Engineer
3 weeks ago
This role is for an FPGA RTL Design Engineer / Senior Engineer to contribute to IP and sub-system development and integration. The ideal candidate will have extensive experience in logic design, RTL coding, and FPGA implementation, with a focus on creating high-performance digital designs and achieving successful FPGA prototyping.
Responsibilities
- Responsible for IP / sub-system level micro-architecture development and RTL coding.
- Prepare block/sub-system level timing constraints.
- Integrate IP/sub-system into larger designs.
- Perform basic verification in either an IP Verification environment or on an FPGA.
Skills
- Expertise in Verilog is a must.
- Experience in Logic design, micro-architecture, and RTL coding is essential.
- Knowledge of AMBA protocols - AXI, AHB, APB.
- Experience in synthesis and a strong understanding of timing concepts in Xilinx FPGA Implementation is required.
- FPGA Proto-typing experience is a must.
- Hands-on experience in Multi Clock designs and Asynchronous interfaces are a must.
- Experience with tools utilized in all phases of ASIC development such as Lint, CDC, Simulation, etc., is required.
- Knowledge of low power concepts and experience is a plus.
- Experience in designing controllers for complex protocols like DDR, USB, or PCIe is a plus.
Qualifications
- A B.Tech. or M.Tech. degree with relevant experience.
- Immediate availability is preferred.
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